Table of Content

30 January 2013, Volume 47 Issue 01 Previous Issue    Next Issue

Radiao Electronics, Telecommunication Technology

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Soft Error Problem and Countermeasure in Nanometer Scale Integrated Circuits   ZHANG Min-Xuan, SUN Yan, SONG Chao 2013, 47 (01):  1-6.  Abstract ( 2382 )   Save This paper described the mechanism, trends and evaluation techniques of soft errors in nanometer scale integrated circuits. For solving the soft error problems, the paper summed up the countermeasures across the software level, circuit and architecturelevel as well as process devicelevel. At last,  some suggestions on the development of related studies on soft error problems were put forward.   References | Related Articles | Metrics

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Finite Target Oriented Collisionless Radio Frequency Identification Technology LI Xiao-Fang, ZHANG Min-Xuan, XU Wei-Xia 2013, 47 (01):  7-12.  Abstract ( 2017 )   Save An FDMA (frequency division multiple access) based finite target oriented collisionless RFID (radio frequency identification) technology was proposed to solve the identification of multitarget. RFID systems based on the proposed technology have strong points such as collisionless, high speed, and high sensitivity, and are especially applicable to applications such as electronic article surveillance (EAS), infant school management, and so on. Technology of RFID tag design was studied and identification algorithm was introduced, and a set of simulative experiments were carried out. The results of simulative experiments prove the correctness of the proposed technology and techniques. References | Related Articles | Metrics

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Novel Structure of Buffer: Support Deadlock-Free Fully-Adaptive Routing XIAO Can-Wen, ZHANG Min-Xuan 2013, 47 (01):  13-17.  Abstract ( 2503 )   Save For the wormhole switching networks, a novel structure of input buffer called multi-request input buffer organization (MRIBO) was presented. The MRIBO supports Duato’s methodology to realize deadlock-free fully-adaptive routing when packets are interleaved in buffer. The performance of MRIBO was analyzed on the BookSim simulator developed at the Standford University. The simulation results show that the performance of MRBO is superior to the FIFO buffer organization, with nearly 68% reduction in the packets latency for uniform traffic. Key words： References | Related Articles | Metrics

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A Fault-Tolerant and Deadlock-Free Routing Algorithm in2D-Mesh for Network on Chip ZHOU Lei-1, 2 , WU Ning-1, LI Yun-2 2013, 47 (01):  18-22.  Abstract ( 3122 )   Save A fault-tolerant and deadlock-free routing algorithm applied in 2D-mesh was proposed to solve the problem of the permanent and unpredictable failure occurrence in network on chip. Firstly a new definition of fault block is proposed to reduce the region of fault and the affected healthy node, and then a detour-path construction algorithm is designed to implement the construction of fault block and the generation of detour-path list by recursive of message deliver. The detour-path routing algorithm combines the detour-path list and routing rules, makes a detour to avoid the fault block by adding detour-path list into the header flit. The experimental results show that the proposed algorithm achieves a reduction of average delay under uniform random distribution and hotspot distribution.   References | Related Articles | Metrics

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Design and Realization of Wireless Clock Distribution Transmitter Based on Folded Antennas Integrated on Silicon Substrate LI Jin-Wen, HE Xiao-Wei, ZHANG Min-Xuan 2013, 47 (01):  23-27.  Abstract ( 2067 )   Save Based on wireless interconnect technique using antennas integrated on silicon substrate and electromagnetic waves, a transmitter of wireless clock distribution for microprocessors was designed and realized. It consists of a 2.6 mm long, 30 μm wide folded dipole antenna integrated on 10 Ω·cm silicon substrate, a high frequency phase locking loop (PLL), driving and matching circuits. The on-chip folded antenna utilizes chip area effectively, and its transmission gain is improved by employing diamond between silicon substrate and heat sink. The central frequency of the proposed PLL is 11 GHz, and simulated phase noise achieves -116 and -127 dBc/Hz at 3 and 10 MHz offset, respectively. Impedance matching between antenna and circuit is performed in order to reduce transmission power loss. The simulated results indicate that this transmitter occupies 0.85 mm2 effective area, which can provide low jitter, stable high frequency global clock. References | Related Articles | Metrics

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Design of a Reconfigurable Parallel Nonlinear Feedback Shift Register Structure Targeted at Stream Cipher CHEN Tao-1, YANG Xuan-2, DAI Zi-Bin-1, LI Wei-1, CHEN Xun-1 2013, 47 (01):  28-32.  Abstract ( 2839 )   Save A reconfigurable parallel hardware structure targeted at nonlinear feedback shift register (NFSR) was proposed. As to the reconfigurable performance, the structure could reconfigure different NFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel update of NFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibility and high performance, the paper adopted reconfigurable and parallel technology to design an NFSR hardware structure, the thesis synthesized the design in 0.18 μm CMOS (complementary metal-oxide-semiconductor transistor) process. The result proves that the critical path of reconfigurable feedback shift register with 256 lengths, 32 parallelizability is 5.8 ns, the throughput rate can achieve 5.5 Gb/s.   References | Related Articles | Metrics

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Effect of Device Size on Pulse Quenching in a 65 nm Bulk CMOS Process LI Peng, ZHAO Zhen-Yu, ZHENG Chao, ZHANG Min-Xuan 2013, 47 (01):  33-38.  Abstract ( 2116 )   Save The connection between the size of passive inverter and trend of pulse quenching was studied by using circuit level simulation under 65nm bulk complementary metaloxidesemiconductor transistor (CMOS) process. It is found that bipolar amplification plays an important role in pulse quenching trend after changing the size of passive inverter. Pulse quenching will be zoomed in after increasing the size of passive inverter, whose inner bipolar amplification is stronger. In the contrast, pulse quenching will be zoomed out after increasing the size of passive inverter. References | Related Articles | Metrics

Automation Technique, Computer Technology

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Reliability-Aware Link Management Strategy for Network on Chip JIAO Jia-Jia, FU Yu-Zhuo 2013, 47 (01):  39-43.  Abstract ( 2952 )   Save An application specified link management strategy and related routing algorithm was proposed to decrease network on chip (NoC) power consumption and make good use of partially customized advantages with guaranteed performance and reliability, in accordance to  the application communication characteristic and fault tolerant requirements. Taking VOPD for example, the simulation results show that our reliability-aware NoC link management strategy can achieve comprehensive metric more than 30% improvement over the standard Mesh.   References | Related Articles | Metrics

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Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor HAN Xing, JIANG Jiang, FU Yu-Zhuo, ZHOU Chuan, LIU Zi-Yang, YANG Kai-Kai 2013, 47 (01):  44-48.  Abstract ( 2842 )   Save A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced. According to the locality principle, both the hardware support, including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol, and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor. This paper also introduced the simulation platform for dynamically reconfigurable many-core processor, which is developed based on system level simulator Gem 5. The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented. The simulation result proves the improvement for performance of the manycore processor.   References | Related Articles | Metrics

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An Adaptive Token Protocol Optimized for Migratory Sharing FU Gui-Tao-1, 2 , ZHAO Tian-Lei-1, TANG Chuan-1, XING Zuo-Cheng-1 2013, 47 (01):  49-54.  Abstract ( 2270 )   Save According to the migratory pattern means that the accessing processor initiates two separate requests to obtain first read and then write permission in invalidation-based protocol, this paper proposed adaptive protocol which uses the token number and the writer or reader of data to recognize the migratory pattern. While the data is in migratory pattern, the requestor’s state changes to MG state which can avoid the write request in migratory access. It effectively eliminates invalidation in migratory pattern. The adaptive protocol gets the ownership when reading the sharing data, and thus avoids some write misses. The results show that the adaptive protocol reduces the miss latency by an average of 5%, and the network traffic by an average of 9%.   References | Related Articles | Metrics

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Design for Silicon Debug of Integrated Circuit by Reusing Test Logic ZHANG Ming, GAO Jun, ZHANG Min-Xuan 2013, 47 (01):  55-59.  Abstract ( 2040 )   Save  Test logic is often reused by silicon debug during design stage of IC. Based on reusing test logic, two improved structures for silicon debug were proposed, one is that scanning registers in short chains to speedup accesses of focused registers, another is that adding asynchronous debug ports for memory build-in self-test (MBIST) controller, which accelerates accesses of static memory and reduces difficulties of physical design. The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost, and makes debug operations faster. References | Related Articles | Metrics

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Reliability-Aware Optimization for Task Mapping in Network-on-Chip LIU Ting, WU Yao-Yi, FU Yu-Zhuo 2013, 47 (01):  60-64.  Abstract ( 2933 )   Save To meet the increasing demands on reliability of specific applied areas, this paper presented RaNMAP, a reliability-aware task mapping algorithm for network-on-chip(NoC) applications. The RaNMAP was developed from an existing greedy heuristic mapping algorithm called NMAP, by adding a new scheme to define fault tolerant technique based communication cost and set reliability as the constraint. The algorithm was applied with NoC task benchmarks and demostrated an overall reliability improvement under most simulaition conditions. The analysis results show that RaNMAP offers an effective framework for high abstract level fault tolerance aware design and evaluation in NoCs.  References | Related Articles | Metrics

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A 3D Stacking Technology Based Reliable Cache Architecture SUN Yan, SONG Chao, LI Tie-Jun, ZHANG Min-Xuan 2013, 47 (01):  65-69.  Abstract ( 2780 )   Save Focused on soft error issue in 3D integrated circuits, this paper analyzed particles tracks and characters when highenergy particles get into 3D stacking chips, and then presented a kind of 3D stacking technologybased reliable Cache architecture R3DCache after analyzing soft error vulnerability of each component of Caches. The R3DCache can greatly reduce error rate with little area and performance overheads. The analysis results show that the proposed structure can bring down soft error rate of Caches to 5% of original one with 0.52% to 4.17% area overhead, while the performance overhead can be ignored. References | Related Articles | Metrics

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Parallel Processing Mapping Strategy of Spatial Analysis under the Heterogeneous Environment ZHANG Jian-Bo, ZHOU Si-Bo, YUAN Guo-Bin, SHI Yang, ZHU Jian-Bo 2013, 47 (01):  70-75.  Abstract ( 2252 )   Save Aiming at the low efficiency when traditional realization methods of local arithmetic operators of map algebra apply to calculations for gigantic raster data, the realization mechanism from surrounding parallel mapping of serial algorithms and adaptive parameter adjustments on computer graphic processor resources was discussed. The data partition strategy was used to the acceleration of spatial analysis operators. The strategy divides operators into subtasks and maps these subtasks to the graphic processing unit (GPU) for calculation. It overlaps the calculation with data transmission to hide the data transmission time and accelerate operators by using the powerful computation ability of heterogeneous environment. The theoretical analysis and experimental results show that this strategy can significantly improve the processing speed of space analysis operators. References | Related Articles | Metrics

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Automatic Word-Length Determination Tool Based on Simulated Annealing Algorithm LI Yuan-1, JIANG Jiang-2, ZHANG Min-Xuan-1, WEI Shao-Jun-3 2013, 47 (01):  76-80.  Abstract ( 2323 )   Save An automatic word-length determination tool (SATRANS) based on the simulated annealing algorithm was developed. SATRANS can  automatically transform the system from floatingpoint model to fixed-point model and provide a series of word-length solutions that form a tradeoff curve for hardware complexity vs. signal quality. SATRANS was demonstrated to find word-length for an infinite impulse response filter (IIR). The results show that SATRANS can provide better word-length solution in comparison to the traditional search method based on  greedy strategy. The word-length optimized IIR targeting Xilinx Virtex-6 FPGA device was implemented, which improves the performance  by 12.4% and 62.8% while saves almost 93.9% and 97.9% of area in comparison to the IEEE single and double floating-point generators.   References | Related Articles | Metrics

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Data Driven Multi-core Processor BI Zhuo-a, XU Yun-Chuan-b, WANG Zhen-b 2013, 47 (01):  81-85.  Abstract ( 2116 )   Save  For the problem on insufficient parallelism in program of multi-core processors encountered in current technology, a multi-core processor prototype was presented. It supports data driven mechanism and programming style of functional language. The prototype consists of general processor cores, data driven module and router on chip. General processor cores are used to execute normal operation. Data driven module detects the data completeness. Router on chip provides communication among processor cores or clusters. The experimental results show that multi-core processor prototype supports the functional language programming style of C language. The execution of every C code segment is the operation of pure function, which eliminates the sharing variables among functions and partly reduces the complexity of parallel program. Moreover, there are no strict sequential restrictions over the data driven mechanism, which fully excavates the potential parallelism of algorithms. According to the test, the multi-core processors based on data driven mechanism can obtain linear acceleration ratio with the increase of computation source. It preliminarily proves that the acceleration ratio of data flow machine maintains linearly increasing with the increase of processors. References | Related Articles | Metrics

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A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor WANG Di-1, BAI Han-2, ZHAO Tian-Lei-1, TANG Yu-Xing-1, DOU Qiang-1 2013, 47 (01):  86-91.  Abstract ( 2427 )   Save By utilizing silicon via’s characteristics such as short delays and less power consumption, this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies. By analyzing the experimental data the paper proves 3DE-Mesh’s function and scalability. The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.   References | Related Articles | Metrics

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Deadlock Detection and Recovery Based on Topological Order for NoC QIAO Yu-Ran, WU Nan, YANG Qian-Ming, WEN Mei, ZHANG Chun-Yuan 2013, 47 (01):  92-97.  Abstract ( 2759 )   Save A mechanism of deadlock detection and recovery for networks on chip (NoC) which makes use of topological order was proposed. It uses  the characteristics of NoC, which has enough wire sources to use dedicated wires to achieve and analyze the dependence of the channels to locate the positions of deadlocks quickly, and then unlocks the deadlock loops. This mechanism is simple and effective, and it supports various routing algorithms. Compared to deadlock avoiding, it can raise the availability of network resources and increase the tolerance ability. References | Related Articles | Metrics

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Parallel On-line Testing for Digital Microfluidic Biochip ZHANG Ling-1, 2 , KUANG Ji-Shun-2, LIN Jing-3, MEI Jun-Jin-1 2013, 47 (01):  98-102.  Abstract ( 2489 )   Save A new parallel on-line testing scheme for digital microfluidic biochips was proposed. The biochip array under test is divided into same-size sub-arrays first, and these sub-arrays are tested parallel under biochip module placement constraints in the bioassay process. The proposed scheme reduces the number of test droplets and test application time efficiently, and it would not disturb the bioassay process. The experimental results also prove the efficiency of the proposed on-line test scheme. References | Related Articles | Metrics

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A Cache Dynamic Power Analysis Tool in Full-System Simics HUANG Zhi-Bin, ZHU Ming-Fa, XIAO Li-Min 2013, 47 (01):  103-107.  Abstract ( 3244 )   Save A dynamic power analysis tool PowerGC based on Cache behavior for cycle-level full-system simics was proposed. The basic idea is dissembling the Cache behavior into five atomic operations. These operations independently drive the sub-components of data array and tag array, which can be estimated by Cacti 6.5 and support different Cache logic structures and Cache management policies. According to the evaluation results based on Simics, PowerGC works well to estimate the Cache dynamical power for different Cache structures and different management policies. References | Related Articles | Metrics

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Design of a 2 GHz L2 Cache for 16-core Processor LI Yong-Jin, DENG Rang-Yu, YAN Xiao-Bo, YI Xiao-Fei, ZHOU Hong-Wei, ZHANG Ying 2013, 47 (01):  108-112.  Abstract ( 2214 )   Save An L2 Cache design scheme was provided to process the memory access with high efficiency. L2 Cache manages data coherency with L1 Cache by the improved directory protocol, and manages date coherence with other L2 Caches and L3 Caches by cooperating with directory control unit. An MESIAF Cache coherency protocol was implemented. The stage of pipeline is small, so load data can be returned to core in advance. The potential deadlock was resolved by two dependence list. The leakage power is decreased by sleeping the data array and just waking up them before used. The dynamic power is decreased by applying the fine gate clock. The result of backend design shows that the design frequency reaches 2 GHz. The design has been used in a 16-core processor chip successfully. References | Related Articles | Metrics

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Realization and Design of a Hybrid Storage System in High Performance Computing SONG Zhen-Long, LI Qiong, XU Wei-Xia, LI Jin-Wen, LIU Guang-Ming 2013, 47 (01):  113-117.  Abstract ( 2644 )   Save A hybrid storage system with RAM-disk is proposed. It was a novel method which can reduce the latency of I/O by inserting a RAM-disk in the different nodes of the system for caching the I/O files. The result of experiment implies that the hybrid storage system with RAM-disk can improve the performance and availability of file system. References | Related Articles | Metrics

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Low Power Design of a Multi-Core Processor Chip GAO Jun, WANG Yong-Wen, GUO Wei, HUANG An-Wen 2013, 47 (01):  118-122.  Abstract ( 2434 )   Save In order to implement low power design of Cool Symmetry Processor (CSP) which is a high frequency multi-core processor chip, three techniques are proposed for power reduction based on CSP structure, that is interval power gating, dynamic frequency scaling based on throughput and hierarchical clock gating. The results of experiment show the three low power techniques reduce CSP chip power effectively. The interval power gating solves leakage power, the dynamic frequency scaling based on throughput and hierarchical clock gating can control dynamic power.   References | Related Articles | Metrics

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A Synthesizable Pseudo-Random Functional Verification Method for Cache ZHANG Jian-Min, ZHANG Jun, XIA Jun, PANG Zheng-Bin, XU Wei-Xia 2013, 47 (01):  123-128.  Abstract ( 2686 )   Save  For the Cache in the microprocessors, a synthesizable pseudo-random functional verification method was proposed. This method was applied in the real chips, and was compared with the pseudo-random verification method on software simulation in performance. The results show that the method is faster by about three orders of magnitude, and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.   References | Related Articles | Metrics

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Dither Circuit to Improve Performance for a Radiation Hardening by Design Pipeline Analog to Digital Converter YU Jin-Shan-1, 2 , LIANG Sheng-Ming-2, MA Zhuo-1, WANG Yu-Xin-2, ZHANG Rui-Tao-2Liu-Tao-2, LI Ting-2, YU Zhou-2 2013, 47 (01):  129-133.  Abstract ( 2282 )   Save A subtractive dither technology to improve performance for a high-resolution radiation hardening by design pipeline analog-to-digital converter was proposed. The dither signal generation is based on a deep multi-bits pseudo-random number generator driving a 5-bit high-resolution digital to analogue conversion (DAC). This dither signal is added with analog to digital converter (ADC) input signal, sampled, quantized and then digitally subtracted from the ADC output, thereby causing no significant degradation signal noise ratio (SNR). The measured results show that the proposed dither technology can efficiently improve static and dynamic performance of the ADC, especially when the ADC quantizes a small-signal input.   References | Related Articles | Metrics

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Code Isolation Based Iterative Compilation Optimization for Large Programs LU Ping-Jing, LI Bao, CHE Yong-Gang, PANG Zheng-Bin 2013, 47 (01):  133-137.  Abstract ( 2348 )   Save A lightweight large programs optimization method, code isolation based iterative compilation was proposed, which isolated kernel code segments from original scientific and engineering codes, organized them into source files, and then optimized these isolated codes using iterative compilation separately. In this way, different kernel code segments could be optimized with specific optimization configuration; therefore, it optimized programs more effectively and boosted the whole programs’ performance. Meanwhile, the multi-dimensional optimization space was split into several lower-dimensional optimization spaces, and the optimization cost was reduced. The experimental results show that it is a low-weight and easy-to-implement method for large programs, and it is also suitable for general code optimization.   References | Related Articles | Metrics

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High Radix Router Design Based on Asymmetric Crossbar FANG Ming-1, CHEN Song-Qiao-1, WANG Ke-Fei-2 2013, 47 (01):  138-143.  Abstract ( 2454 )   Save Throughput of asymmetric crossbaris was analyzed in theoretical and simulation way. The result reveals that in asymmetric crossbar head of line (HOL) effect can be negligible. A new architecture of high radix router, hierarchical asymmetric crossbar (HAC), which is based on asymmetric crossbar, along with its tile-based microarchitecture, was introduced. The simulation reveals that HAC router can get much high throughput. References | Related Articles | Metrics

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A Flit-Switch Bufferless Router Based on Encoding Allocation SHEN Jian-Liang, QI Shu-Bo, LI Jin-Wen, LIU Lei, LI Si-Kun 2013, 47 (01):  144-148.  Abstract ( 1915 )   Save A flit-switch bufferless router based on encoding allocation (FBEABLESS), was proposed, which can reduce the delay of critical path through two stage switch allocation with non-deflection allocation and deflection allocation. The go-stop-steer (GOSS) strategy was used to avoid livelock in the network. The simulation results show that the average delay decreases about 29.4% in the FBEA-BLESS compared with the baseline bufferless router (BLESS). References | Related Articles | Metrics

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Master-Equation Simulation of Double-Island Single-Electron Transistor Based on Periodical Characteristics SUI Bing-Cai, GAO Jun, CHEN Xiao-Bao, ZHANG Chao, FANG Liang 2013, 47 (01):  149-154.  Abstract ( 2072 )   Save The periodical characteristics of double-island single-electron transistor (SET) were analyzed by stable diagram and Monte-Carlo method. Seven typical states were selected to simplify the masterequation simulation, and to improve the limitation of the method by the periodical characteristics. The result shows that the proposed method can efficiently simulate the current and voltage character of double-island SET, and can be simply extended to multi-island SETs, which is very useful for the VLSI of multi-island SETs.   References | Related Articles | Metrics

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High-Effect Priority Bounded Confidence Model for Network Opinion Evolution CHEN Gui-Rong-1, 2 , CAI Wan-Dong-1, XU Hui-Jie-1, YAN Pei-Xiang-3, WANG Jian-Ping-1 2013, 47 (01):  155-160.  Abstract ( 2967 )   Save Artificial social networks which include thousands of members have become an important platform for network opinion evolution. People will not try their best to get and consider all other people’s opinions when they give their opinions in Internet, because they do not have enough time and energy to do this, and they don’t think it is necessary. But in bounded confidence model, it needs to take into account all the other people’s opinions when any people update his opinion, which is in conflict with the real networks. To solve this problem, a novelty network opinion evolution model with dualchoices based on effect and confidence was proposed, according to human behavioral patterns in real networks, and a model of people’s opinion insistence strategy was made. The new model and the bounded confidence model with different sets of parameters were simulated for many times, and the results are in good agreement with what happened in real networks. References | Related Articles | Metrics

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TCAM and Multi-core Network Processor Cooperative IP Lookup Acceleration Model SHI Wei, LU Ze-Xin, SUN Zhi-Gang 2013, 47 (01):  161-166.  Abstract ( 2358 )   Save This article proposed a ternary content addressable memory (TCAM) and multi-core network processor (NP) cooperated Internet Protocol (IP) lookup acceleration model. The core idea of this model includes three parts. First the routing table entries whose prefix length exceeds 24 are located in TCAM, Secondly, the remaining table entries are structured into a compresses binary tree which is utilized to determine which part to be put into hardware. The other part is located into NP’s level2 cache and their memory indexes are stored in TCAM to accelerate lookup. At last forwarding information is put into static random access memory (SRAM) which reduces the delay of NP’s packet processing at highest degree. The packet processing model has great scalability which cost little incremental storage resources as routing table size expands and with the muti-thread characteristic of NP，the total throughput of our model can reach 100 Gb/s theoretically,which can completely satisfy the forwarding demands of current core routers. Key words： References | Related Articles | Metrics