Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor

Abstract

Abstract: A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced. According to the locality principle, both the hardware support, including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol, and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor. This paper also introduced the simulation platform for dynamically reconfigurable many-core processor, which is developed based on system level simulator Gem 5. The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented. The simulation result proves the improvement for performance of the manycore processor.

Key words: virtual computing group, many-core processor, reconfiguration, Cache coherence, simulation platform

CLC Number:

TP 368

HAN Xing, JIANG Jiang, FU Yu-Zhuo, ZHOU Chuan, LIU Zi-Yang, YANG Kai-Kai. Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 44-48.

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