A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor

Abstract

Abstract: By utilizing silicon via’s characteristics such as short delays and less power consumption, this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies. By analyzing the experimental data the paper proves 3DE-Mesh’s function and scalability. The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.

Key words: three dimensional integrated circuits (3D IC), three dimensional networks-on-chip (3D NoC), topology, extended channel

CLC Number:

TP 391

WANG Di-1, BAI Han-2, ZHAO Tian-Lei-1, TANG Yu-Xing-1, DOU Qiang-1. A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 86-91.

References

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