Abstract: This article proposed a ternary content addressable memory (TCAM) and multi-core network processor (NP) cooperated Internet Protocol (IP) lookup acceleration model. The core idea of this model includes three parts. First the routing table entries whose prefix length exceeds 24 are located in TCAM, Secondly, the remaining table entries are structured into a compresses binary tree which is utilized to determine which part to be put into hardware. The other part is located into NP’s level2 cache and their memory indexes are stored in TCAM to accelerate lookup. At last forwarding information is put into static random access memory (SRAM) which reduces the delay of NP’s packet processing at highest degree. The packet processing model has great scalability which cost little incremental storage resources as routing table size expands and with the muti-thread characteristic of NP，the total throughput of our model can reach 100 Gb/s theoretically,which can completely satisfy the forwarding demands of current core routers. Key words：

Key words: ternary content addressable memory (TCAM), multi-core network processor (NP), acceleration model, delay