[1]YI Maoxiang, LIANG Huaguo,WANG Wei, et al. A core union test scheme for reducing system on chip test time[J]. Journal of Shanghai Jiaotong University, 2010, 41(11):223228.[2]Rahmani A M, Liljeberg P, Plosila J, et al. Efficient 3D NoC architecture using bidirectional synchronous vertical channels [C]∥Symposium on ISVLSI. Turku, Finland: IEEE Computer Society, 2010: 452453.[3]Murali S, Seiculescu C, Benini L, et al. Synthesis of networks on chips for 3D systems on chips [C]∥Asia and South Pacific Design Automation Conference. Yokohama, Japan: IEEE Computer Society, 2009: 242247.[4]Glass J, Ni L M. Faulttolerant wormhole routing in meshes without virtual channels [J]. IEEE Transactions on Parallel and Distribution Systems, 1996(12): 942951.[5]Ge F, Wu N, Wan Y P. A network monitor based dynamic routing scheme for network on chip [C]∥Proceedings of IEEE Prime Asia. Macao, China: IEEE Computer Society, 2009: 133136.[6]Zhang Z, Greiner A, Taktak S. A reconfigurable routing algorithm for a fault tolerant 2Dmesh network on chip [C]∥Proceedings of the 45th Design Automation Conference. New York, USA: IEEE Computer Society, 2008:441446.[7]Hu W M, Lu Z H, Jantsch A, et al. A flexible configuration approach for faulttolerant multicast/unicast [C]∥Proceedings of CommUnication Software and Networks. Changsha, China: IEEE Computer Society, 2011: 393396.[8]Noxim. NetworkonChip Simulator [EB/OL].[20120701] . http:∥sourceforge.net/projectsnoxim.[9]Holsmark R, Kumar S. Corrections to chen and chiu’s fault tolerant routing algorithm for mesh networks [J]. Journal of Information Science and Engineering, 2007, 23(6): 16491662. |