Abstract: Based on wireless interconnect technique using antennas integrated on silicon substrate and electromagnetic waves, a transmitter of wireless clock distribution for microprocessors was designed and realized. It consists of a 2.6 mm long, 30 μm wide folded dipole antenna integrated on 10 Ω·cm silicon substrate, a high frequency phase locking loop (PLL), driving and matching circuits. The on-chip folded antenna utilizes chip area effectively, and its transmission gain is improved by employing diamond between silicon substrate and heat sink. The central frequency of the proposed PLL is 11 GHz, and simulated phase noise achieves -116 and -127 dBc/Hz at 3 and 10 MHz offset, respectively. Impedance matching between antenna and circuit is performed in order to reduce transmission power loss. The simulated results indicate that this transmitter occupies 0.85 mm2 effective area, which can provide low jitter, stable high frequency global clock.

Key words: folded antenna, wireless interconnect, phase locking loop (PLL), transmission gain