Abstract: A reconfigurable parallel hardware structure targeted at nonlinear feedback shift register (NFSR) was proposed. As to the reconfigurable performance, the structure could reconfigure different NFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel update of NFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibility and high performance, the paper adopted reconfigurable and parallel technology to design an NFSR hardware structure, the thesis synthesized the design in 0.18 μm CMOS (complementary metal-oxide-semiconductor transistor) process. The result proves that the critical path of reconfigurable feedback shift register with 256 lengths, 32 parallelizability is 5.8 ns, the throughput rate can achieve 5.5 Gb/s.  

Key words: stream cipher, nonlinear feedback shift register (NFSR), reconfigurable, parallel