A Synthesizable Pseudo-Random Functional Verification Method for Cache

Abstract

Abstract: For the Cache in the microprocessors, a synthesizable pseudo-random functional verification method was proposed. This method was applied in the real chips, and was compared with the pseudo-random verification method on software simulation in performance. The results show that the method is faster by about three orders of magnitude, and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.

Key words: Cache, functional verification, pseudorandom stimulus, hardware emulation

CLC Number:

TP 333

ZHANG Jian-Min, ZHANG Jun, XIA Jun, PANG Zheng-Bin, XU Wei-Xia. A Synthesizable Pseudo-Random Functional Verification Method for Cache[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 123-128.

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