Design for Silicon Debug of Integrated Circuit by Reusing Test Logic

Abstract

Abstract: Test logic is often reused by silicon debug during design stage of IC. Based on reusing test logic, two improved structures for silicon debug were proposed, one is that scanning registers in short chains to speedup accesses of focused registers, another is that adding asynchronous debug ports for memory build-in self-test (MBIST) controller, which accelerates accesses of static memory and reduces difficulties of physical design. The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost, and makes debug operations faster.

Key words: silicon debug, scan chain, memory build-in self-test (MBIST)

CLC Number:

TP 333

ZHANG Ming, GAO Jun, ZHANG Min-Xuan. Design for Silicon Debug of Integrated Circuit by Reusing Test Logic[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 55-59.

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