Low Power Design of a Multi-Core Processor Chip

Abstract

Abstract: In order to implement low power design of Cool Symmetry Processor (CSP) which is a high frequency multi-core processor chip, three techniques are proposed for power reduction based on CSP structure, that is interval power gating, dynamic frequency scaling based on throughput and hierarchical clock gating. The results of experiment show the three low power techniques reduce CSP chip power effectively. The interval power gating solves leakage power, the dynamic frequency scaling based on throughput and hierarchical clock gating can control dynamic power.

Key words: chip, power, power gating, dynamic frequency scaling (DFS), clock gating

CLC Number:

TP 302.1

GAO Jun, WANG Yong-Wen, GUO Wei, HUANG An-Wen. Low Power Design of a Multi-Core Processor Chip[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 118-122.

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