Reliability Modelling and Prediction Method for Phase Change Memory Using Optimal Pulse Conditions

doi:10.1007/s12204-020-2153-8

Abstract

Abstract: Phase change memory (PCM) has reached the level of mass production. The first step in mass production is determining the proper pulse conditions of high-resistance (HR) and low-resistance (LR) states to realize the best performance of PCM chips on the basis of longer endurance characteristics. However, due to the neglect of each of the relations as well as the square term of each relationship for pulse conditions, the standard screening method for pulse conditions cannot accurately determine the optimal pulse conditions. A new statistical prediction method based on regression analysis is presented in this work. The method can model and predict the optimal pulse conditions of PCM chips on the basis of longer endurance characteristics. In the method, the parameter estimates, model equations and surface plot are generated by the least-mean-square (LMS) method for the regression analysis; the prediction model is established by monitoring the distributions of the resistance values collected from a 4 Kbit block of the 4 Mbit PCM test chips in 40 nm complementary metal oxide semiconductor (CMOS) process.

Key words: phase change memory (PCM)| prediction model| regression analysis| pulse conditions

摘要： Phase change memory (PCM) has reached the level of mass production. The first step in mass production is determining the proper pulse conditions of high-resistance (HR) and low-resistance (LR) states to realize the best performance of PCM chips on the basis of longer endurance characteristics. However, due to the neglect of each of the relations as well as the square term of each relationship for pulse conditions, the standard screening method for pulse conditions cannot accurately determine the optimal pulse conditions. A new statistical prediction method based on regression analysis is presented in this work. The method can model and predict the optimal pulse conditions of PCM chips on the basis of longer endurance characteristics. In the method, the parameter estimates, model equations and surface plot are generated by the least-mean-square (LMS) method for the regression analysis; the prediction model is established by monitoring the distributions of the resistance values collected from a 4 Kbit block of the 4 Mbit PCM test chips in 40 nm complementary metal oxide semiconductor (CMOS) process.

关键词: phase change memory (PCM)| prediction model| regression analysis| pulse conditions

CLC Number:

TN 3
O 213

YAN Shuai (闫帅), CAI Daolin (蔡道林), CHEN Yifeng (陈一峰), XUE Yuan (薛媛), LIU Yuanguang (刘源广), WU Lei (吴磊), SONG Zhitang (宋志棠). Reliability Modelling and Prediction Method for Phase Change Memory Using Optimal Pulse Conditions[J]. Journal of Shanghai Jiao Tong University (Science), 2020, 25(1): 1-9.

References 17

[1]	WUTTIG M, YAMADA N. Phase-change materials for rewriteable data storage [J]. Nature Materials,2007, 6(11): 824-832.
[2]	RAOUX S, BURR G W, BREITWISCH M J, et al. Phase-change random access memory: A scalable technology [J]. IBM Journal of Research and Development,2008, 52(4/5): 465-479.
[3]	BEZ R. Chalcogenide PCM: A memory technology for next decade [C]//2009 IEEE International Electron Devices Meeting (IEDM). Baltimore, MD, USA:IEEE, 2009: 11207415.
[4]	WONG H S P, RAOUX S, KIM S B, et al. Phase change memory [J]. Proceedings of the IEEE, 2010,98(12): 2201-2227.
[5]	WANG Y, GUO T Q, LIU G Y, et al. Sc-centered octahedron enables high-speed phase change memory with improved data retention and reduced power consumption [J]. ACS Applied Materials & Interfaces, 2019,11(11): 10848-10855.
[6]	RAO F, DING K Y, ZHOU Y X, et al. Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing [J]. Science, 2017,358(6369): 1423-1427.
[7]	WANG Y Q, CAI D L, CHEN Y F, et al. Optimizing set performance for phase change memory with dual pulses set method [J]. ECS Solid State Letters, 2015,4(7): 32-35.
[8]	PIROVANO A, REDAELLI A, PELLIZZER F, et al. Reliability study of phase-change nonvolatie memories[J]. IEEE Transactions on Device and Materials Reliability, 2004, 4(3): 422-427.
[9]	RAOUX S. Phase change materials [J]. Annual Review of Materials Research, 2009, 39: 25-48.
[10]	OTTOGALLI F, PIROVANO A, PELLIZZER F, et al. Phase-change memory technology for embedded applications [C]//Proceedings of the 30th European Solid-State Circuits Conference. Leuven, Belgium: IEEE, 2004: 293-296.
[11]	WANG Y Q, CAI D L, CHEN Y F, et al. Reduction of reset current in phase change memory by preprogramming [J]. ECS Journal of Solid State Science and Technology, 2016, 5(2): 13-16.
[12]	SANDRE G D, BETTINI L, PIROLA A, et al. A 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology [J]. IEEE Journal of Solid-State Circuits, 2011, 46(1): 52-63.
[13]	CAI D L, CHEN H P, WANG Q, et al. An 8-Mb phase-change random access memory chip based on a resistor-on-via-stacked-plug storage cell [J]. IEEE Electron Device Letters, 2012, 33(9): 1270-1272.
[14]	KANG D H, KIM J S, KIM Y R, et al. Novel heat dissipating cell scheme for improving a reset distribution in a 512M phase-change random access memory (PRAM) [C]//2007 IEEE Symposium on VLSI Technology. Kyoto, Japan: IEEE, 2007: 96-97.
[15]	SHIH Y H, LEE M H, BREITWISCH M, et al. Understanding amorphous states of phase-change memory using Frenkel-Poole model [C]//2009 IEEE International Electron Devices Meeting (IEDM). Baltimore,MD, USA: IEEE, 2009: 753-756.
[16]	CALDERONI A, FERRO M, VARESI E, et al. Understanding overreset transition in phase-change memory characteristics [J]. IEEE Electron Device Letters, 2012, 33(9): 1267-1269.
[17]	BRAGA S, CABRINI A, TORELLI G. Experimental analysis of partial-SET state stability in phase-change memories [J]. IEEE Transactions on Electron Devices, 2011, 58(2): 517-522.