A Simple Method to Solve the Network Congestion for Spitial Architcture

doi:10.1007/s12204-017-1802-z

Abstract

Abstract: Scheduling algorithm always plays an important role in the spatial architecture for the contradiction between the finite network bandwidth and the abundant execution resources. This article provides a simple method to solve the contention for network resource in one of the spatial architecture, i.e. the tera-op, reliable, intelligently adaptive processing system (TRIPS) processor. The method improves the performance of network by increasing the bypass bandwidth which can transmit the data in the internal of every execution unit, and converting the proportion of remote communication by the deep scheduling algorithm. The deeply optimized algorithm is realized to verify the validity of the method, and the performance increase 9% for floating point spec2000 benchmark is got.

Key words: scheduling algorithm| spatial architecture| processor| network contention

摘要： Scheduling algorithm always plays an important role in the spatial architecture for the contradiction between the finite network bandwidth and the abundant execution resources. This article provides a simple method to solve the contention for network resource in one of the spatial architecture, i.e. the tera-op, reliable, intelligently adaptive processing system (TRIPS) processor. The method improves the performance of network by increasing the bypass bandwidth which can transmit the data in the internal of every execution unit, and converting the proportion of remote communication by the deep scheduling algorithm. The deeply optimized algorithm is realized to verify the validity of the method, and the performance increase 9% for floating point spec2000 benchmark is got.

关键词: scheduling algorithm| spatial architecture| processor| network contention

CLC Number:

TP 302.7

ZHANG Chao* (张超), YU Mingyan (喻明艳), YANG Bing (杨兵). A Simple Method to Solve the Network Congestion for Spitial Architcture[J]. Journal of shanghai Jiaotong University (Science), 2017, 22(1): 72-076.

References 13

[1]	NOWATZKI T, SARTIN-TARMM, CARLI L D, et al.A General Constraint-centric Scheduling Frameworkfor Spatial Architectures [C]//Proceedings of the 34thAnnual ACMSIGPLAN Conference on ProgrammingLanguage Design and Implementation. Seattle, USA:ACM, 2013: 1-12.
[2]	WAINGOLD E, TAYLOR M, SRIKRISHNA D, et al.Baring it all to software: Raw machines [J]. Computer,1997, 30(9): 86-93.
[3]	SWANSON S, MICHELSON K, SCHWERIN A, et al.Wavescalar [C]//Proceedings of the 36th InternationalSymposium on Microarchitecture. [s.l.]: IEEE, 2003: 1-12.
[4]	BURGER D, KECKLER S W, MCKINLEY K S, et al.Scaling to the end of silicon with EDGE architectures[J]. IEEE Computer, 2004, 37(7): 44-55.
[5]	WATKINS M A, CIANCHETTI M J, ALBONESID H. Shared reconfigurable architectures for CMPs.[C]//International Conference on Field ProgrammableLogic & Applications. [s.l.]: IEEE, 2008: 299-304.
[6]	GOVINDARAJU V, HO C H, NOWATZKI T, et al.Dyser: Unifying functionality and parallelism specializationfor energy efficient computing [J]. IEEE Micro,2012, 33(5): 38-50.
[7]	ESMAEILZADEH H, SAMPSON A, CEZE L, et al.Neural acceleration for general-purpose approximateprograms [J]. IEEE Micro, 2013, 33(3): 16-27.
[8]	NAGARAJAN R, KUSHWAHA S K, BURGER D, etal. Static placement, dynamic issue (SPDI) schedulingfor edge architectures [C]//Proceedings of the 13thInternational Conference on Parallel Architecture andCompilation Techniques. [s.l.]: IEEE, 2004: 74-84.
[9]	GRATZ P, SANKARALINGAM K, HANSON H, etal. Implementation and evaluation of a dynamicallyrouted processor operand network [C]//Proceedings ofthe First International Symposium on Networks-on-Chip. [s.l.]: IEEE, 2007: 7-17
[10]	COONS K E, CHEN X, KUSHWAHA S K, et al.A spatial path scheduling algorithm for EDGE architectures[C]//Proceedings of the 12th InternationalConference on Architectural Support for ProgrammingLanguages and Operating Systems. [s.l.]: IEEE, 2006:129-140.
[11]	GOU P F, LI Q B, JIN Y H, et al. M5 based edge architecturemodeling [C]//Proceedings of IEEE InternationalConference on Computer Design. Netherlands:Amsterdam: IEEE, 2010: 289- 296.
[12]	ROBATMILI B, COONS K E, BURGER D, et al.Strategies for mapping dataflow blocks to distributedhardware [C]//In International Symposium on Microarchitecture.[s.l.]: IEEE, 2008: 23-34.
[13]	KIM C, SETHUMADHAVAN S, GOVINDAN M S, etal. Composable lightweight processors [C]// In InternationalSymposium on Microarchitecture. [s.l.]: IEEE,2007: 381-394.

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