Journal of Shanghai Jiaotong University ›› 2018, Vol. 52 ›› Issue (9): 1098-1103.doi: 10.16183/j.cnki.jsjtu.2018.09.014

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A Design of Low Power Audio Noise Reduction Processor for Smart Microphone

CHEN Liming,CHEN Chengying,YANG Jun   

  1. 1. School of Opto-Electronic and Communication Engineering, Xiamen University of Technology, Xiamen 361024, Fujian, China; 2. Foshan University, Foshan 528000, Guangdong, China

Abstract: A low power noise reduction processor is developed to improve SNR of microphone. The processor consists of ASIP (application specific instruction-set processor) and hardware accelerators, achieving a great tradeoff of power, efficiency and flexibility. The ASIP has 24-bit width, multi-step pipeline, dual Harvard memory architecture. Acceleration instructions are developed to improve computation efficiency. The reconfigurable accelerators are introduced for high density computing tasks, such as the transformation between time and frequency domain. The processor is implemented on SMIC 130 nm technology, and results show that the processor reduces the noise by 10 dB, consuming about 206 μA current on average.

Key words: application specific instruction-set processor, audio signal processing, digital signal processors, low power electronics, micro-electro-mechanical system microphone

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