Abstract: This paper proposed an improved decoder structure which can be applied to any irregular quasicyclic low density parity check (LDPC) codes. The decoder needs only one shuffle network by adjusting the memory cells of the RAM. The pipeline conflicts due to the irregular LDPC codes can be solved by properly inserting idle clocks and preprocess of the low density parity check matrix. Meanwhile, such decoding process still achieves high throughput and suffers little decoder performance loss.