An Accuracy Dynamically Configurable FFT Processor Based on Approximate Computing

doi:10.16183/j.cnki.jsjtu.2020.430

Abstract

Abstract:

In order to meet the different requirements of circuit targets in various scenarios, an accuracy configurable fast Fourier transform (FFT) processor based on the concept of approximate circuit is proposed. A configurable approximate butterfly unit which can truncate the carry chain is proposed at the butterfly node and a bit-width configurable multiplier is proposed at the rotation factor multiplication node. MATLAB is adopted to develop an error analysis platform. After analyzing the sensitivity of each butterfly node and rotation factor node to approximate calculations, five calculation modes of the accuracy configurable FFT processor are determined, which can achieve dynamic balance among performance, power consumption, and accuracy. Finally, based on the 180 nm complementary metal oxide semiconductor (CMOS) technology of Taiwan Semiconductor Manufacturing Company (TSMC), the proposed processor is implemented with the standard procedure of ultra-large-scale digital integrated circuits. The performance results are obtained by professional electronic design automation (EDA) tools. Compared with the precise mode, the maximum operating frequency of the processor in the approximate mode is increased by 14.33%, and the power consumption is reduced by 15.61% when the operating frequency is 60 MHz.

Key words: approximate circuit, fast Fourier transform (FFT), accuracy dynamically configurable, approximate butterfly computation unit, bit-width configurable

CLC Number:

TN47

MA Liping, ZHANG Xiaoyu, BAI Yuxin, CHEN Xin, ZHANG Ying. An Accuracy Dynamically Configurable FFT Processor Based on Approximate Computing[J]. Journal of Shanghai Jiao Tong University, 2022, 56(2): 223-230.

Figures/Tables 12

Fig.1

Fig.2

Tab.1

Fig.3

Tab.2

Rotation factor ranges of each multiplication node

乘法节点	旋转因子
1	$W 80$ ~ $W 83$
2	$W 80$ 、 $W 82$
3	$W 5120$ ~ $W 512441$
4	$W 80$ ~ $W 83$
5	$W 80$ 、 $W 82$
6	$W 640$ ~ $W 6449$
7	$W 80$ ~ $W 83$
8	$W 80$ 、 $W 82$

Tab.2

Fig.4

Fig.5

Tab.3

Fig.6

Fig.7

Tab.5

Fig.8

References 10

[1]	VENKATESAN R, AGARWAL A, ROY K, et al. MACACO: Modeling and analysis of circuits for approximate computing[C]//2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, CA, USA: IEEE, 2011: 667-673.
[2]	MITRA S K. 数字信号处理: 基于计算机的方法[M]. 余翔宇. 第4版.北京: 电子工业出版社, 2012.
	MITRA S K. Digital signal processing: A computer-based approach[M]. YU Xiangyu. 4th ed. Beijing: Publishing House of Electronics Industry, 2012.
[3]	LIU S H, LIU D K. A high-flexible low-latency memory-based FFT processor for 4G, WLAN, and future 5G[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(3):511-523. doi: 10.1109/TVLSI.2018.2879675 URL
[4]	PASHAEIFAR M, KAMAL M, AFZALI-KUSHA A, et al. Approximate reverse carry propagate adder for energy-efficient DSP applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(11):2530-2541. doi: 10.1109/TVLSI.2018.2859939 URL
[5]	BECHER A, ECHAVARRIA J, ZIENER D, et al. A LUT-based approximate adder [C]//2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Piscataway, NJ, USA: IEEE, 2016: 27.
[6]	LINGAMNENI A, ENZ C, PALEM K, et al. Highly energy-efficient and quality-tunable inexact FFT accelerators [C]//Proceedings of the IEEE 2014 Custom Integrated Circuits Conference. San Jose, CA, USA: IEEE, 2014: 1-4.
[7]	LIU W Q, LIAO Q C, QIAO F, et al. Approximate designs for fast Fourier transform (FFT) with application to speech recognition[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(12):4727-4739. doi: 10.1109/TCSI.8919 URL
[8]	XIAO H, YIN X, WU N, et al. VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors[J]. IET Computers & Digital Techniques, 2018, 12(3):105-110. doi: 10.1049/cdt2.v12.3 URL
[9]	YANG K J, TSAI S H, CHUANG G C H. MDC FFT/IFFT processor with variable length for MIMO-OFDM systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 21(4):720-731. doi: 10.1109/TVLSI.2012.2194315 URL
[10]	KALA S, NALESH S, NANDY S K, et al. Energy efficient, scalable, and dynamically reconfigurable FFT architecture for OFDM systems [C]//2014 Fifth International Symposium on Electronic System Design. Surathkal, India: IEEE, 2014: 20-24.

蝶形节点9的j值	各蝶形节点j值的选取 (蝶形节点1~9排列)
0	(4, 3, 3, 3, 2, 2, 1, 1, 0)
1	(4, 3, 3, 3, 2, 2, 1, 1, 1)
2	(4, 3, 3, 3, 2, 2, 2, 2, 2)
3	(4, 3, 3, 3, 3, 3, 3, 3, 3)
4	(4, 4, 4, 4, 4, 4, 4, 4, 4)
5	(5, 5, 5, 5, 5, 5, 5, 5, 5)
6	(6, 6, 6, 6, 6, 6, 6, 6, 6)
7	(7, 7, 7, 7, 7, 7, 7, 7, 7)

模式	九级蝶形模块的j值 (从模块1~9)	w_mul	Q_PDP	S_sqnr
精确	(0, 0, 0, 0, 0, 0, 0, 0, 0)	14	11.33	55.49
近似0	(0, 0, 0, 0, 0, 0, 0, 0, 0)	10	9.34	51.88
近似1	(3, 3, 3, 3, 2, 2, 1, 1, 1)	10	8.89	49.45
近似2	(3, 3, 3, 3, 2, 2, 2, 2, 2)	10	9.20	46.12
近似3	(3, 3, 3, 3, 3, 3, 3, 3, 3)	8	8.67	37.26

已发表的 FFT文献	本文设计的FFT 不同工作模式	FFT点数	工艺/nm	工作电压/V	输入位宽	S_sqnr/dB
—	精确模式	512	180	1.8	16	55.51
—	近似0					51.62
—	近似1					49.06
—	近似2					45.98
—	近似3					37.45
文献[10]	—	2048	90	1	8	40
文献[9]	—	4096	65	1.2	16	51
文献[8]	—	8192	130	1.2	10	53.28
最大工作频率/MHz	数据通路	面积/mm²	归一化面积	功耗/mW	归一化能耗	测试结果
128.4	1	2.07	230.0	30.26@60 MHz	91.48	EDA工具功耗评估
128.4				27.51@60 MHz	83.16
134.0				27.50@60 MHz	83.13
140.4				27.50@60 MHz	83.13
146.8				25.53@60 MHz	77.18
250	4	3.1	282.8	63.72@40 MHz	117.29	实测
125	1	1.05	671.0	33.5@40 MHz	157.03	实测
400	1	2.7	398.2	35.7@40 MHz	107.79	实测