A 10-bit 500 kHz low-power successive approximation register (SAR) analog-to-digital converter
(ADC) for cryogenic infrared readout circuit is proposed. To improve the simulation accuracy of metal-oxidesemiconductor
field-effect transistors (MOSFETs), corresponding modification in device model is presented on the
basis of BSIM3v3 with parameter extraction at 77K. Corresponding timing is adopted in comparator to eliminate
the influence caused by abnormal performance of MOSFETs at 77 K. The SAR ADC is fabricated and verified
by standard 0.35 μm complementary metal oxide semiconductor (CMOS) process. At 77 K, measurement results
show that signal to noise and distortion ratio (SNDR) is 54.74 dB and effective number of bits (ENOB) is 8.8 at
the sampling rate of 500 kHz. The total circuit consumes 0.6mW at 3.3V power supply.
ZHAO Yi-qiang1* (赵毅强), YANG Ming1 (杨 明), ZHAO Hong-liang2 (赵宏亮)
. A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model[J]. Journal of Shanghai Jiaotong University(Science), 2013
, 18(5)
: 520
-525
.
DOI: 10.1007/s12204-013-1436-8
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