Abstract: Circuit net list bipartitioning using
simulated annealing technique has been proposed in the paper. The
method converges asymptotically and probabilistically to global
optimization. The circuit net list is partitioned into two
partitions such that the number of interconnections between the
partitions is minimized. The proposed method begins with an
innovative clustering technique to obtain a good initial solution.
Results obtained show the versatility of the proposed method in
solving non polynomial hard problems of circuit net list
partitioning and show an improvement over those available in
literature.

Key words:

cut size| non polynomial hard| partitioning|
simulated annealing| interconnections| very large scale integration
(VLSI) design

摘要： Circuit net list bipartitioning using
simulated annealing technique has been proposed in the paper. The
method converges asymptotically and probabilistically to global
optimization. The circuit net list is partitioned into two
partitions such that the number of interconnections between the
partitions is minimized. The proposed method begins with an
innovative clustering technique to obtain a good initial solution.
Results obtained show the versatility of the proposed method in
solving non polynomial hard problems of circuit net list
partitioning and show an improvement over those available in
literature.

关键词:

cut size| non polynomial hard| partitioning|
simulated annealing| interconnections| very large scale integration
(VLSI) design