Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

doi:10.1007/s12204-017-1862-0

Journal of shanghai Jiaotong University (Science) ›› 2017, Vol. 22 ›› Issue (4): 493-503.doi: 10.1007/s12204-017-1862-0

Previous Articles Next Articles

Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

SHAN Rui1* (山蕊), LI Tao2 (李涛), JIANG Lin3 (蒋林),DENG Junyong3 (邓军勇), SHEN Xubang1 (沈绪榜)

(1. School of Microelectronics, Xidian University, Xi’an 710071, China; 2. Research Center for ASIC Design, Xi’an University of Posts and Telecommunications, Xi’an 710121, China; 3. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China)
(1. School of Microelectronics, Xidian University, Xi’an 710071, China; 2. Research Center for ASIC Design, Xi’an University of Posts and Telecommunications, Xi’an 710121, China; 3. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China)

Online:2017-08-03 Published:2017-08-03
Contact: SHAN Rui (山蕊) E-mail:shanrui0112@163.com

Abstract

Abstract: Abstract: The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.

Key words: reconfigurable architecture| cell array| dataflow computing| storage structure| distributed storage

摘要： Abstract: The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.

关键词: reconfigurable architecture| cell array| dataflow computing| storage structure| distributed storage

CLC Number:

TP 391

SHAN Rui1* (山蕊), LI Tao2 (李涛), JIANG Lin3 (蒋林),DENG Junyong3 (邓军勇), SHEN Xubang1 (沈绪榜). Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array[J]. Journal of shanghai Jiaotong University (Science), 2017, 22(4): 493-503.

References 16

[1]	SMITH M C, PETERSON G D. Optimization ofshared high-performance reconfigurable computing resources[J]. ACM Transactions on Embedded ComputingSystems, 2012, 11(2): 36.
[2]	MIYAMORI T, OLUKOTUN K. A Quantitative analysisof reconfigurable coprocessors for multimedia applications[C]//IEEE Symposium on FPGAs for CustomComputing Machines. [s.l.]: IEEE, 1998: 2-11.
[3]	SINGH H, LEE M H, LU G M, et al. MorphoSys: Anintegrated reconfigurable system for data-parallel andcomputation-intensive applications [J]. IEEE Transactionson Computers, 2000, 49(5): 465-481.
[4]	VEREDAS F J, SCHEPPLER M, MOFFAT W, et al.Custom implementation of the coarse-grained reconfigurableADRES architecture for multimedia purposes[C]//International Conference on Field ProgrammableLogic and Applications. [s.l.]: IEEE, 2005: 106-111.
[5]	PACT XPP Technologies. XPP-III processor overview[EB/OL]. (2006-07-13). http://www.pactxpp.com.
[6]	ZHU M, LIU L B, YIN S Y, et al. A reconfigurablemulti-processor SoC for media applications [C]//IEEEInternational Symposium on Circuits and Systems.[s.l.]: IEEE, 2010: 2011-2014.
[7]	LI T, XIAO L Z, HUANG H C, et al. PAAG: A polymorphicarray architecture for graphics and image processing[C]//International Symposium on Parallel Architectures,Algorithms and Programming. [s.l.]: IEEE,2012: 242-249.
[8]	COMPTON K, HAUCK S. Reconfigurable computing:A survey of systems and software [J]. ACM ComputingSurveys, 2002, 34(2): 171-210.
[9]	AMANO H. A survey on dynamically reconfigurableprocessors [J]. IEICE Transactions on Communications,2006, 89 (12): 3179-3187.
[10]	NAJJAR W A, LEE E A, GAO G R. Advances in thedataflow computational model [J]. Parallel Computing,2000, 25(13/14): 1907-1929.
[11]	ROSENFELD J, FRIEDMAN E G. Design methodologyfor global resonant H-tree clock distribution networks[J]. IEEE Transactions on Very Large Scale IntegrationSystems, 2007, 15(2): 135-148.
[12]	Khronos Vision Working Group. The OpenVXspecification [EB/OL]. (2014-10-07). https://www.khronos.org/registry/vx/specs/1.0.1/html/index.html.
[13]	HOGENAUER E B. An economical class of digital filtersfor decimation and interpolation [J]. IEEE Transactionson Acoustics Speech and Signal Processing,1981, 29(2): 155-162.
[14]	MONSON J, WIRTHLIN M, HUTCHINGS B L. Optimizationtechniques for a high level synthesis implementationof the Sobel filter [C]//2013 InternationalConference on IEEE Reconfigurable Computing andFPGAs (ReConFig). [s.l.]: IEEE, 2013: 1-6.
[15]	SHAN R, LI T, HAN J G. The buffered edge reconfigurablecell array and its applications [C]//201312th IEEE International Conference on Trust, Securityand Privacy in Computing and Communications.[s.l.]: IEEE, 2013: 1023-1030.
[16]	DORE A, LASRADO S. Performance analysis of Sobeledge filter on heterogeneous system using OPENCL[J]. International Journal of Research in Engineeringand Technology, 2014, 3(15): 53-57.

Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

Design and Implementation of a Data-Driven Dynamical Reconfigurable Cell Array

PDF (PC)

Knowledge

Abstract

Cite this article

share this article

References 16

Related Articles 6

Recommended Articles

Metrics

Comments

[1]	XU Liangye, SHI Lianxing, SHAN Rongsheng. A Consistency Checking Method for Erasure-Coded Striped Data [J]. Journal of Shanghai Jiao Tong University, 2024, 58(4): 579-584.
[2]	YOU Lijue, JIAO Shengpin, LI Xiaoyong. Optimization of Data Storage Performance in Medical PACS Imaging System [J]. Journal of Shanghai Jiao Tong University, 2024, 58(10): 1629-1636.
[3]	WANG Jing, LI Jinghui, YANG Jiarong, WANG E. Construction of Optimal Locally Repairable Codes of Triangular Association Schemes [J]. Journal of Shanghai Jiao Tong University, 2024, 58(10): 1596-1605.
[4]	SHAN Rui (山蕊), JIANG Lin (蒋林), WU Haoyue (吴昊玥), HE Feilong (贺飞龙), LIU Xinchuang (刘新闯). Dynamical Self-Reconfigurable Mechanism for Data-Driven Cell Array [J]. J Shanghai Jiaotong Univ Sci, 2021, 26(4): 511-521.
[5]	CAO Peng,MEI Chen，LIU Bo. Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application [J]. Journal of Shanghai Jiaotong University, 2014, 48(10): 1389-1393.
[6]	LIU Zhen-tao1* (刘镇弢), LI Tao2 (李涛), HAN Jun-gang2 (韩俊刚). A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing [J]. Journal of shanghai Jiaotong University (Science), 2013, 18(3): 348-359.