上海交通大学学报(英文版) ›› 2013, Vol. 18 ›› Issue (3): 348-359.doi: 10.1007/s12204-013-1405-2
LIU Zhen-tao1* (刘镇弢), LI Tao2 (李 涛), HAN Jun-gang2 (韩俊刚)
出版日期:
2013-06-28
发布日期:
2013-08-12
通讯作者:
LIU Zhen-tao (刘镇弢)
E-mail: liuzhentao@xupt.edu.cn
LIU Zhen-tao1* (刘镇弢), LI Tao2 (李 涛), HAN Jun-gang2 (韩俊刚)
Online:
2013-06-28
Published:
2013-08-12
Contact:
LIU Zhen-tao (刘镇弢)
E-mail: liuzhentao@xupt.edu.cn
摘要: This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine (FSM) controllers. Each cluster contains various kinds of cells that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.
中图分类号:
LIU Zhen-tao1* (刘镇弢), LI Tao2 (李 涛), HAN Jun-gang2 (韩俊刚). A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing[J]. 上海交通大学学报(英文版), 2013, 18(3): 348-359.
LIU Zhen-tao1* (刘镇弢), LI Tao2 (李 涛), HAN Jun-gang2 (韩俊刚). A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing[J]. Journal of shanghai Jiaotong University (Science), 2013, 18(3): 348-359.
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