A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

doi:10.1007/s12204-013-1405-2

上海交通大学学报（英文版） ›› 2013, Vol. 18 ›› Issue (3): 348-359.doi: 10.1007/s12204-013-1405-2

A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

LIU Zhen-tao1* (刘镇弢), LI Tao2 (李涛), HAN Jun-gang2 (韩俊刚)

(1. School of Microelectronics, Xidian University, Xi’an 710071, China; 2. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China)

出版日期:2013-06-28 发布日期:2013-08-12
通讯作者: LIU Zhen-tao (刘镇弢) E-mail: liuzhentao@xupt.edu.cn

A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

LIU Zhen-tao1* (刘镇弢), LI Tao2 (李涛), HAN Jun-gang2 (韩俊刚)

(1. School of Microelectronics, Xidian University, Xi’an 710071, China; 2. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China)

Online:2013-06-28 Published:2013-08-12
Contact: LIU Zhen-tao (刘镇弢) E-mail: liuzhentao@xupt.edu.cn

摘要/Abstract

摘要： This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine (FSM) controllers. Each cluster contains various kinds of cells that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.

关键词: dynamically reconfigurable architecture, data-flow, video stream processing, augmented finite state machine

Abstract: This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine (FSM) controllers. Each cluster contains various kinds of cells that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.

Key words: dynamically reconfigurable architecture, data-flow, video stream processing, augmented finite state machine

中图分类号:

TP 391

LIU Zhen-tao1* (刘镇弢), LI Tao2 (李涛), HAN Jun-gang2 (韩俊刚). A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing[J]. 上海交通大学学报（英文版）, 2013, 18(3): 348-359.

LIU Zhen-tao1* (刘镇弢), LI Tao2 (李涛), HAN Jun-gang2 (韩俊刚). A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing[J]. Journal of shanghai Jiaotong University (Science), 2013, 18(3): 348-359.

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A Novel Reconfigurable Data-Flow Architecture for Real Time Video Processing

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