Electronic Information and Electrical Engineering

A Circuit Simulation Model of 1S1R for 3D Phase-Change Memory

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  • 1. School of Microelectronics, University of Science and Technology of China, Hefei 230026, China
    2. Shanghai Nanotechnology Promotion Center, Shanghai 200237, China
    3. Shanghai Institute of Microsystem and Information Technology of Chinese Academy of Sciences, Shanghai 200050, China

Received date: 2021-12-21

  Online published: 2022-06-22

Abstract

The 1S1R storage unit of 3D phase-change memory is composed of ovonic threshold switch selector (OTS) in series with the phase change memory (PCM) device. In order to solve the problems of the current OTS and PCM circuit simulation models, such as not able to accurately simulate the electrical and physical characteristics of devices, and not suitable for confined PCM, a 1S1R spice model based on Verilog-A is proposed. The model simulates the electrical characteristics of OTS and the changes of current, temperature, melting proportion, crystallization proportion and amorphous proportion in the crystallization, melting and quenching of the PCM. The model has a good convergence and fast simulation speed. The simulation results are consistent with the actual test results of the device. Compared with the traditional model, the simulation and integration of confined PCM melting process, crystal nonlinearity, melting resistivity stability and subthreshold nonlinearity, and bidirectional switching characteristics of OTS are realized. The relationship between OTS subthreshold nonlinear parameter and read voltage window is analyzed. It is found that the read window reaches its maximum when OTS threshold current is approximately equal to PCM threshold current. The results of DC simulation of 1S1R cell and transient simulation of array are displayed, providing the basis for circuit design and simulation of 3D phase-change memory.

Cite this article

ZHANG Guangming, LEI Yu, CHEN Houpeng, YU Qiuyao, SONG Zhitang . A Circuit Simulation Model of 1S1R for 3D Phase-Change Memory[J]. Journal of Shanghai Jiaotong University, 2022 , 56(12) : 1649 -1657 . DOI: 10.16183/j.cnki.jsjtu.2021.522

References

[1] RAO F, DING K Y, ZHOU Y X, et al. Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing[J]. Science, 2017, 358(6369): 1423-1427.
[2] 李晓云, 陈后鹏, 雷宇, 等. 一种基于相变存储器的高速读出电路设计[J]. 上海交通大学学报, 2019, 53(8): 936-942.
[2] LI Xiaoyun, CHEN Houpeng, LEI Yu, et al. A high-speed read circuit for phase-change random-access memory[J]. Journal of Shanghai Jiao Tong University, 2019, 53(8): 936-942.
[3] SONG Z T, CAI D L, LI X, et al. High endurance phase change memory chip implemented based on carbon-doped Ge2Sb2Te5 in 40 nm node for embedded application[C]//IEEE International Electron Devices Meeting. San Francisco, California, USA: IEEE, 2018: 27.5. 1-27.5.4.
[4] 吴磊, 蔡道林, 陈一峰, 等. 连续性RESET/SET对相变存储器疲劳特性的影响[J]. 上海交通大学学报, 2021, 55(9): 1134-1141.
[4] WU Lei, CAI Daolin, CHEN Yifeng, et al. Impact of continuous RESET/SET operations on endurance characteristic of phase change memory[J]. Journal of Shanghai Jiao Tong University, 2021, 55(9): 1134-1141.
[5] XIE C C, LI X, LEI Y, et al. BIST-based fault diagnosis for PCM with enhanced test scheme and fault-free region finding algorithm[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(7): 1652-1664.
[6] ZHU M, REN K, SONG Z T. Ovonic threshold switching selectors for three-dimensional stackable phase-change memory[J]. MRS Bulletin, 2019, 44(9): 715-720.
[7] NOé P, VERDY A, D’ACAPITO F, et al. Toward ultimate nonvolatile resistive memories: The mechanism behind ovonic threshold switching revealed[J]. Science Advances, 2020, 6(9): 2830.
[8] CHENG H Y, CARTA F, CHIEN W C, et al. 3D cross-point phase-change memory for storage-class memory[J]. Journal of Physics D: Applied Physics, 2019, 52(47): 473002.
[9] CHOI J T, AN B K, KIM T T H, et al. Development of PCM and OTS macro-models for HSPICE compatible simulation[C]//Electron Devices Technology and Manufacturing Conference. Singapore: IEEE, 2019: 463-465.
[10] CHEN X H, DING F L, HUANG X Q, et al. A robust and efficient compact model for phase-change memory circuit simulations[J]. IEEE Transactions on Electron Devices, 2021, 68(9): 4404-4410.
[11] CHEN Z Q, TONG H, CAI W, et al. Modeling and simulations of the integrated device of phase change memory and ovonic threshold switch selector with a confined structure[J]. IEEE Transactions on Electron Devices, 2021, 68(4): 1616-1621.
[12] CHEN X H, HU H F, HUANG X Q, et al. A SPICE model of phase change memory for neuromorphic circuits[J]. IEEE Access, 2020, 8: 95278-95287.
[13] PIGOT C, BOCQUET M, GILIBERT F, et al. Comprehensive phase-change memory compact model for circuit simulation[J]. IEEE Transactions on Electron Devices, 2018, 65(10): 4282-4289.
[14] SONODA K, SAKAI A, MONIWA M, et al. A compact model of phase-change memory based on rate equations of crystallization and amorphization[J]. IEEE Transactions on Electron Devices, 2008, 55(7): 1672-1681.
[15] WOO J, YU S M. Design space exploration of ovonic threshold switch (OTS) for sub-threshold read operation in cross-point memory arrays[C]//IEEE International Symposium on Circuits and Systems. Sapporo, Japan: IEEE, 2019: 1-5.
[16] YOO S, LEE H D, LEE S, et al. Electro-thermal model for thermal disturbance in cross-point phase-change memory[J]. IEEE Transactions on Electron Devices, 2020, 67(4): 1454-1459.
[17] TITIRSHA T, SONG S H, DAS A, et al. Endurance-aware mapping of spiking neural networks to neuromorphic hardware[J]. IEEE Transactions on Parallel and Distributed Systems, 2022, 33(2): 288-301.
[18] CHEN W C, YIN W Y, LI E P, et al. Electrothermal investigation on vertically aligned single-walled carbon nanotube contacted phase-change memory array for 3-D ICs[J]. IEEE Transactions on Electron Devices, 2015, 62(10): 3258-3263.
[19] HU H F, LIU D Y, CHEN X H, et al. A compact phase change memory model with dynamic state variables[J]. IEEE Transactions on Electron Devices, 2020, 67(1): 133-139.
[20] FAZIO A. Advanced technology and systems of cross point memory[C]//IEEE International Electron Devices Meeting. San Francisco, CA, USA: IEEE, 2020: 24.1. 1-24.1.4.
[21] XIONG F, BAE M H, DAI Y, et al. Self-aligned nanotube-nanowire phase change memory[J]. Nano Letters, 2013, 13(2): 464-469.
[22] SCOGGIN J, SILVA H, GOKIRMAK A. Field dependent conductivity and threshold switching in amorphous chalcogenides—Modeling and simulations of ovonic threshold switches and phase change memory devices[J]. Journal of Applied Physics, 2020, 128(23): 234503.
[23] CIL K, DIRISAGLIK F, ADNANE L, et al. Electrical resistivity of liquid Ge2Sb2Te5 based on thin-film and nanoscale device measurements[J]. IEEE Transactions on Electron Devices, 2013, 60(1): 433-437.
[24] KIM S, KIM H D, CHOI S J. Intrinsic threshold switching responses in AsTeSi thin film[J]. Journal of Alloys and Compounds, 2016, 667: 91-95.
[25] LIU D Y, ZHANG L N, LIN X N, et al. A smooth and continuous phase change memory SPICE model for improved convergence[C]//IEEE 2nd Electron Devices Technology and Manufacturing Conference. Kobe, Japan: IEEE, 2018: 86-88.
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