Abstract: An extended pattern runlength (xPRL) coding approach was introduced, which uses a dynamic don’t care bit propagation strategy to improve test data compression. Multiple core test sets for testing system on chip (SoC) are merged into a single data stream and compressed by the xPRL coding. A reconfigurable serial scan chain was designed to make the test vectors of different cores unionapplicable. The proposed scheme was applied to an example of SoC with six large ISCAS’89 benchmarks embedded. The analysis and experimental results show that compared to the previous techniques, in which a test set is compressed and applied independently of others, our technique can increase compression rate and, at the same time, reduce redundant shift and capture cycles during scan testing, which thereby can effectively reduce test application time of SoCs.