A High-Speed Read Circuit for Phase-Change Random-Access Memory

doi:10.16183/j.cnki.jsjtu.2019.08.007

Abstract

Abstract: The read circuit in phase-change random access memory (PCRAM) is improved to effectively accelerate the memory’s read speed. By reducing the output voltage swing of the sense amplifier in read circuit, output voltages can reach the intersection point earlier than before, so that can decrease the read access time. Based on SMIC 40nm complementary metal oxide semiconductor (CMOS) process, the novel high-speed sense amplifier is verified at an 8Mb PCRAM chip. The simulation results show that the read speeds of the novel circuit and the conventional circuit both are less than 1 ns when the Ge2Sb2Te5 (GST) resistance in set state (low resistance after set operation) is read. And the read speed can be accelerated more than 35.0% in the novel circuit compared to the conventional read circuit when the GST resistance in reset state (high resistance after set operation) is read. Monte Carlo simulation (the GST resistance in reset state) shows a 58ns worst read access time compared to the conventional circuit 111ns. And the read correctness of the novel read circuit was simulated in this paper. The simulation results show that the read validity can reach 98.8% in the worst reset resistance case (RGST=500kΩ).

Key words: phase-change random access memory (PCRAM); read circuit; sense amplifier (SA); bit line clamp circuit; high-speed

CLC Number:

TN 702

LI Xiaoyun,CHEN Houpeng,LEI Yu,LI Xi,WANG Qian,SONG Zhitang. A High-Speed Read Circuit for Phase-Change Random-Access Memory[J]. Journal of Shanghai Jiaotong University, 2019, 53(8): 936-942.

References

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