Journal of Shanghai Jiaotong University ›› 2019, Vol. 53 ›› Issue (8): 936-942.doi: 10.16183/j.cnki.jsjtu.2019.08.007

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A High-Speed Read Circuit for Phase-Change Random-Access Memory

LI Xiaoyun 1,2,CHEN Houpeng 1,LEI Yu 1,2,LI Xi1,WANG Qian 1,SONG Zhitang 1   

  1. 1. Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences; State Key Laboratory of Functional Materials for Informatics, Shanghai 200050, China; 2. University of Chinese Academy of Sciences, Beijing 100049, China
  • Online:2019-08-28 Published:2019-09-10

Abstract: The read circuit in phase-change random access memory (PCRAM) is improved to effectively accelerate the memory’s read speed. By reducing the output voltage swing of the sense amplifier in read circuit, output voltages can reach the intersection point earlier than before, so that can decrease the read access time. Based on SMIC 40nm complementary metal oxide semiconductor (CMOS) process, the novel high-speed sense amplifier is verified at an 8Mb PCRAM chip. The simulation results show that the read speeds of the novel circuit and the conventional circuit both are less than 1 ns when the Ge2Sb2Te5 (GST) resistance in set state (low resistance after set operation) is read. And the read speed can be accelerated more than 35.0% in the novel circuit compared to the conventional read circuit when the GST resistance in reset state (high resistance after set operation) is read. Monte Carlo simulation (the GST resistance in reset state) shows a 58ns worst read access time compared to the conventional circuit 111ns. And the read correctness of the novel read circuit was simulated in this paper. The simulation results show that the read validity can reach 98.8% in the worst reset resistance case (RGST=500kΩ).

Key words: phase-change random access memory (PCRAM); read circuit; sense amplifier (SA); bit line clamp circuit; high-speed

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