一种高速缓冲存储器的可综合伪随机功能验证方法

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 123-128.

• 自动化技术、计算机技术 • 上一篇下一篇

一种高速缓冲存储器的可综合伪随机功能验证方法

张建民，张峻，夏军，庞征斌，徐炜遐

(国防科学技术大学计算机学院，长沙 410073)

收稿日期:2012-05-17 出版日期:2013-01-30 发布日期:2013-01-30
基金资助:
国家自然科学基金项目(61103083,61133007), 国家高技术研究发展计划项目（863）项目 (2012AA01A301)资助

A Synthesizable Pseudo-Random Functional Verification Method for Cache

ZHANG Jian-Min, ZHANG Jun, XIA Jun, PANG Zheng-Bin, XU Wei-Xia

(College of Computer, National University of Defense Technology, Changsha 410073, China)

Received:2012-05-17 Online:2013-01-30 Published:2013-01-30

摘要/Abstract

摘要： 针对微处理器的高速缓冲存储器（Cache），提出了一种可综合的伪随机功能验证方法，对其在实际芯片中的性能进行测试，并与常见的基于软件模拟的随机功能验证方法进行了对比.结果表明，与基于软件模拟的伪随机功能验证方法相比，所提出的可综合伪随机验证方法的处理速度快约3个数量级，并且能够发现更多的功能错误.

关键词: 高速缓冲存储器, 功能验证, 伪随机激励, 硬件仿真

Abstract: For the Cache in the microprocessors, a synthesizable pseudo-random functional verification method was proposed. This method was applied in the real chips, and was compared with the pseudo-random verification method on software simulation in performance. The results show that the method is faster by about three orders of magnitude, and can find more bugs in the designs in comparison to the pseudo-random verification method on software simulation.

Key words: Cache, functional verification, pseudorandom stimulus, hardware emulation

中图分类号:

TP 333

张建民, 张峻, 夏军, 庞征斌, 徐炜遐. 一种高速缓冲存储器的可综合伪随机功能验证方法[J]. 上海交通大学学报（自然版）, 2013, 47(01): 123-128.

ZHANG Jian-Min, ZHANG Jun, XIA Jun, PANG Zheng-Bin, XU Wei-Xia. A Synthesizable Pseudo-Random Functional Verification Method for Cache[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 123-128.

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一种高速缓冲存储器的可综合伪随机功能验证方法

A Synthesizable Pseudo-Random Functional Verification Method for Cache

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