[1]Benini L, De Micheli G. Networks on chips: A new SoC paradigm [J]. IEEE Comput, 2002, 35(1):7078. [2]Hoskote Y, Vangal S, Singh A, et al. A 5 GHz mesh interconnect for a tera_ops processor [J]. IEEE Micro, 2007, 27 (5): 5161. [3]Wentzlaff D, Griffin P, Hoffmann H, et al. Onchip interconnection architecture of the tile processor [J]. IEEE Micro, 2007, 27 (5): 1531. [4]Murali S, De Micheli G. SUNMAP: A tool for automatic topology selection and generation for NoCs[C]∥ 41st Conference on Design Automation Conference. California, USA: IEEE, 2004:914919. [5]Refan F, Alemzadeh H, Safari S, et al. Reliability in application specific meshbased NoC architecture [C]∥ Proc 14th IEEE International on Line Testing Symposium. Rhodes: IEEE, 2008:207212. [6]Jiao J J, FuY Z, WuY Y. Mutliapplication specified link removal strategy for network on chip[C]∥IEEE International Conference on CSO. Kunming: IEEE, 2011:520524. [7]Wang D, Matsutani H, Amano H, et al. A link removal methodology for networksonchip on reconfigurable systems [C]∥ Proceedings of FPL’08. Heidelberg, Germany: IEEE, 2008: 269274. [8]Jiao J J, Fu Y Z. B2RAC: A physical link addition methodology for network on chip [C]∥ Proceedings of the 4th International Workshop on Network on Chip Architectures. New York: ACM, 2011:1722. [9]Baumann R. Radiationinduced soft errors in advanced semiconductor technologies [J].
Device and Materials Reliability, 2005, 5 (3): 305316. [10]Yu Q Y, Zhang M L,Ampadu P. Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration [C]∥ Fifth IEEE/ACM International Symposium on Networks on Chip (NoCS). Pittsburgh: IEEE, 2011:105112. [11]Chang Y C, Chiu C T, Lin S Y, et al. On the design and analysis of fault tolerant NoC architecture using spare routers[C]∥ Design Automation Conference 2011 16th Asia and South Pacific. Yokohama: IEEE, 2011: 431436. [12]Glass C J, Ni L M. The turn model for adaptive routing [C]∥ Proceedings of the 19th Annual International Symposium on Computer Architecture. New York: ACM, 1992: 278287. [13]Lavina J. A simulator for NoC interconnect routing and application modeling [EB/OL].[20120530]. http:∥nirgam.ecs.soton.ac.uk/. [14]Kahng A B, Li B, Peh L S, et al. ORION 2.0: A fast and accurate NoC power and area model for earlystage design space exploration [C]∥ Proceedings of the Conference on DATE. Leuven, Belgium: ACM, 2009: 423428. [15]Jiao J J, Fu Y Z, Jiang J. Architecturelevel analysis and evaluation of transient errors on NoC [C]∥ 29th NorChip. Lund: IEEE, 2011: 14. |