可靠性感知的片上网络链路管理策略

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 39-43.

• 自动化技术、计算机技术 • 上一篇下一篇

可靠性感知的片上网络链路管理策略

焦佳佳，付宇卓

（上海交通大学微电子学院，上海 200240）

收稿日期:2012-05-30 出版日期:2013-01-30 发布日期:2013-01-30
基金资助:
国家高技术研究发展计划（863）项目(2009AA012201), 美国Cisco大学研究计划201190403（

Reliability-Aware Link Management Strategy for Network on Chip

JIAO Jia-Jia, FU Yu-Zhuo

(School of Microelectronics, Shanghai Jiaotong University, Shanghai 200240, China)

Received:2012-05-30 Online:2013-01-30 Published:2013-01-30

摘要/Abstract

摘要： 在保证片上网络通信性能和可靠性的条件下，根据应用的通信可预测特性和容错需求，提出了可靠性感知的片上网络链路关闭策略，设计了对应的路由算法.同时，以典型的多媒体应用VOPD为例，与无链路管理配置的Mesh结构加以对比，以验证面向应用可靠性感知的片上网络链路管理策略的有效性和可行性.结果表明，所提出的可靠性感知的片上网络链路管理策略不仅可以充分发挥部分定制的优势，而且可以关闭选择的链路和对应的端口时钟，从而节省了片上网络的功耗开销，并获得30%的综合指标收益.

关键词: 片上网络, 链路管理, 可靠性感知, 功耗优化

Abstract: An application specified link management strategy and related routing algorithm was proposed to decrease network on chip (NoC) power consumption and make good use of partially customized advantages with guaranteed performance and reliability, in accordance to the application communication characteristic and fault tolerant requirements. Taking VOPD for example, the simulation results show that our reliability-aware NoC link management strategy can achieve comprehensive metric more than 30% improvement over the standard Mesh.

Key words: network on chip (NoC), link management, reliabilityaware, power optimization

中图分类号:

TP 368

焦佳佳, 付宇卓. 可靠性感知的片上网络链路管理策略[J]. 上海交通大学学报（自然版）, 2013, 47(01): 39-43.

JIAO Jia-Jia, FU Yu-Zhuo. Reliability-Aware Link Management Strategy for Network on Chip[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 39-43.

参考文献

［1］Benini L, De Micheli G. Networks on chips: A new SoC paradigm ［J］. IEEE Comput, 2002, 35(1):7078.
［2］Hoskote Y, Vangal S, Singh A, et al. A 5 GHz mesh interconnect for a tera_ops processor ［J］. IEEE Micro, 2007, 27 (5): 5161.
［3］Wentzlaff D, Griffin P, Hoffmann H, et al. Onchip interconnection architecture of the tile processor ［J］. IEEE Micro, 2007, 27 (5): 1531.
［4］Murali S, De Micheli G. SUNMAP: A tool for automatic topology selection and generation for NoCs［C］∥ 41st Conference on Design Automation Conference. California, USA: IEEE, 2004:914919.
［5］Refan F, Alemzadeh H, Safari S, et al. Reliability in application specific meshbased NoC architecture ［C］∥ Proc 14th IEEE International on Line Testing Symposium. Rhodes: IEEE, 2008:207212.
［6］Jiao J J, FuY Z, WuY Y. Mutliapplication specified link removal strategy for network on chip［C］∥IEEE International Conference on CSO. Kunming: IEEE, 2011:520524.
［7］Wang D, Matsutani H, Amano H, et al. A link removal methodology for networksonchip on reconfigurable systems ［C］∥ Proceedings of FPL’08. Heidelberg, Germany: IEEE, 2008: 269274.
［8］Jiao J J, Fu Y Z. B2RAC: A physical link addition methodology for network on chip ［C］∥ Proceedings of the 4th International Workshop on Network on Chip Architectures. New York: ACM, 2011:1722.
［9］Baumann R. Radiationinduced soft errors in advanced semiconductor technologies ［J］.

Device and Materials Reliability, 2005, 5 (3): 305316.
［10］Yu Q Y, Zhang M L,Ampadu P. Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration ［C］∥ Fifth IEEE/ACM International Symposium on Networks on Chip (NoCS). Pittsburgh: IEEE, 2011:105112.
［11］Chang Y C, Chiu C T, Lin S Y, et al. On the design and analysis of fault tolerant NoC architecture using spare routers［C］∥ Design Automation Conference 2011 16th Asia and South Pacific. Yokohama: IEEE, 2011: 431436.
［12］Glass C J, Ni L M. The turn model for adaptive routing ［C］∥ Proceedings of the 19th Annual International Symposium on Computer Architecture. New York: ACM, 1992: 278287.
［13］Lavina J. A simulator for NoC interconnect routing and application modeling ［EB/OL］.［20120530］. http:∥nirgam.ecs.soton.ac.uk/.
［14］Kahng A B, Li B, Peh L S, et al. ORION 2.0: A fast and accurate NoC power and area model for earlystage design space exploration ［C］∥ Proceedings of the Conference on DATE. Leuven, Belgium: ACM, 2009: 423428.
［15］Jiao J J, Fu Y Z, Jiang J. Architecturelevel analysis and evaluation of transient errors on NoC ［C］∥ 29th NorChip. Lund: IEEE, 2011: 14.

[1]	刘婷, 乌耀益, 付宇卓. 片上网络任务映射算法的可靠性优化 [J]. 上海交通大学学报（自然版）, 2013, 47(01): 60-64.
[2]	周磊1, 2, 吴宁1, 李云2. 一种基于2D-mesh的片上网络无死锁容错路由算法[J]. 上海交通大学学报（自然版）, 2013, 47(01): 18-22.
[3]	王谛1, 白晗2, 赵天磊1, 唐遇星1, 窦强1. 一种面向三维微处理器的新型片上网络拓扑 [J]. 上海交通大学学报（自然版）, 2013, 47(01): 86-91.
[4]	乔寓然, 伍楠, 杨乾明, 文梅, 张春元. 片上网络中基于拓扑排序的死锁检测与恢复方法[J]. 上海交通大学学报（自然版）, 2013, 47(01): 92-97.
[5]	赵智慧,肖石林,梁铮,瞿科锋,刘智鑫. 3种改进的基于光丢失方法的链路资源发现机制[J]. 上海交通大学学报（自然版）, 2010, 44(02): 234-0237.

可靠性感知的片上网络链路管理策略

Reliability-Aware Link Management Strategy for Network on Chip

可视化

摘要/Abstract

引用本文

使用本文

参考文献

相关文章 5

编辑推荐

Metrics

本文评价