动态可重构众核处理器仿真平台设计

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 44-48.

• 自动化技术、计算机技术 • 上一篇下一篇

动态可重构众核处理器仿真平台设计

韩兴，蒋江，付宇卓，周川，刘子扬，杨凯凯

（上海交通大学微电子学院, 上海 200240）

收稿日期:2012-05-30 出版日期:2013-01-30 发布日期:2013-01-30
基金资助:
国家高技术研究发展计划（863）项目(2009AA012201), IBM共享大学研究项目(SUR201102X)

Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor

HAN Xing, JIANG Jiang, FU Yu-Zhuo, ZHOU Chuan, LIU Zi-Yang, YANG Kai-Kai

(School of Microelectronics, Shanghai Jiaotong University, Shanghai 200240, China)

Received:2012-05-30 Online:2013-01-30 Published:2013-01-30

摘要/Abstract

摘要： 针对众核处理器，提出了一种基于计算资源划分机制的动态可重构技术.该技术以虚拟计算群为核心，设计了基于硬件支持的动态可重构子网划分和动态可重构的Cache一致性协议以及动态在线的计算资源调度算法，并对系统级多核仿真平台Gem 5进行了扩展.同时，采用实际测试结果验证了众核处理器中动态可重构技术的有效性.结果表明，动态可重构技术可以提高众核处理器的资源利用率,实现动态可重构的Cache一致性协议以及单一矩形物理子网覆盖的子网划分机制.

关键词: 虚拟计算群, 众核处理器, 可重构, Cache一致性, 仿真平台

Abstract: A dynamic reconfiguration technique based on the partitioning of computing resources on many-core processor was introduced. According to the locality principle, both the hardware support, including dynamically reconfigurable sub-netting in NoC and dynamically reconfigurable Cache coherence protocol, and the scheduling algorithm for on-chip computing resources are designed to improve the utilization of the many-core processor. This paper also introduced the simulation platform for dynamically reconfigurable many-core processor, which is developed based on system level simulator Gem 5. The Cache coherence protocol with sub-netting and scheduling algorithm mentioned above was implemented. The simulation result proves the improvement for performance of the manycore processor.

Key words: virtual computing group, many-core processor, reconfiguration, Cache coherence, simulation platform

中图分类号:

TP 368

韩兴, 蒋江, 付宇卓, 周川, 刘子扬, 杨凯凯. 动态可重构众核处理器仿真平台设计 [J]. 上海交通大学学报（自然版）, 2013, 47(01): 44-48.

HAN Xing, JIANG Jiang, FU Yu-Zhuo, ZHOU Chuan, LIU Zi-Yang, YANG Kai-Kai. Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor[J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 44-48.

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动态可重构众核处理器仿真平台设计

Design of System Level Simulation Platform for Dynamic Reconfigurable Many-Core Processor

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