上海交通大学学报

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 28-32.

• 无线电电子学、电信技术 • 上一篇    下一篇

面向序列密码的非线性反馈移位寄存器可重构并行化设计  

陈韬1，杨萱2，戴紫彬1，李伟1，陈迅1   

  1. （1. 解放军信息工程大学, 郑州 450004； 2. 江南计算技术研究所， 江苏 无锡 214083）
  • 收稿日期:2012-05-16 出版日期:2013-01-30 发布日期:2013-01-30
  • 基金资助:

    国家自然科学基金项目（60903220），国家高技术研究发展计划（863）项目（2009AA012201

Design of a Reconfigurable Parallel Nonlinear Feedback Shift Register Structure Targeted at Stream Cipher

 CHEN  Tao-1, YANG  Xuan-2, DAI  Zi-Bin-1, LI  Wei-1, CHEN  Xun-1   

  1. （1. PLA Information Engineering University, Zhengzhou 450004, China; 2. Jiangnan Institute of Technology, Wuxi 214083, Jiangsu, China）
  • Received:2012-05-16 Online:2013-01-30 Published:2013-01-30

摘要：   摘要： 
基于序列密码的非线性反馈移位寄存器，将可重构技术与并行化处理相融合，提出了一种非线性反馈移位寄存器的可重构并行化架构.结果表明：可重构并行化架构能够灵活重构任意结构的非线性反馈移位寄存器；并行化思想能够支持在一个时钟周期完成对非线性反馈移位寄存器的并行更新；在0.18 μm的互补金属氧化物半导体（CMOS）工艺中，其核心工作频率能够达到172 MHz，针对256级的线性反馈移位寄存器，当并行度选取为32时，其吞吐率能够达到5.5 Gb/s. 关键词： 
序列密码； 非线性反馈移位寄存器； 可重构； 并行化 中图分类号：  TN 492
文献标志码：  A    

Abstract: A reconfigurable parallel hardware structure targeted at nonlinear feedback shift register (NFSR) was proposed. As to the reconfigurable performance, the structure could reconfigure different NFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel update of NFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibility and high performance, the paper adopted reconfigurable and parallel technology to design an NFSR hardware structure, the thesis synthesized the design in 0.18 μm CMOS (complementary metal-oxide-semiconductor transistor) process. The result proves that the critical path of reconfigurable feedback shift register with 256 lengths, 32 parallelizability is 5.8 ns, the throughput rate can achieve 5.5 Gb/s.  

Key words: stream cipher, nonlinear feedback shift register (NFSR), reconfigurable, parallel