纳米级集成电路的软错误问题及其对策

摘要/Abstract

摘要： 介绍了纳米级集成电路中软错误的发生机制、发展趋势以及评估技术，概括了软件、电路和体系结构以及工艺器件级软错误的缓解对策，并针对软错误问题相关研究的发展提出几点建议.

Abstract: This paper described the mechanism, trends and evaluation techniques of soft errors in nanometer scale integrated circuits. For solving the soft error problems, the paper summed up the countermeasures across the software level, circuit and architecturelevel as well as process devicelevel. At last, some suggestions on the development of related studies on soft error problems were put
forward.

Key words: soft error, integrated circuits, reliability

中图分类号:

TN 47

张民选, 孙岩, 宋超. 纳米级集成电路的软错误问题及其对策 [J]. 上海交通大学学报（自然版）, 2013, 47(01): 1-6.

ZHANG Min-Xuan, SUN Yan, SONG Chao. Soft Error Problem and Countermeasure in Nanometer Scale Integrated Circuits [J]. Journal of Shanghai Jiaotong University, 2013, 47(01): 1-6.

参考文献

［1］

Mitra S, Seifert N, Zhang M, et al. Robust system design with builtin softerror resilience ［J］. IEEE Transactions on Computer, 2005, 38 (2): 4352.
［2］Shivakumar P, Kistler M, Keckler S W, et al. Modeling the effect of technology trends on the soft error rate of combinational logic ［C］∥International Conference on Dependable Systems and Networks. Maryland: IEEE, 2002: 389398.
［3］Mukherjee M. Architecture design for soft errors ［M］. Amsterdam: Elsevier, 2008: 13.
［4］黄海林, 唐志敏, 许彤. 龙芯1号处理器的故障注入方法与软错误敏感性分析［J］. 计算机研究与发展, 2006, 43 (10): 18201827.
HUANG Hailin, TANG Zhimin, XU Tong. Fault injection and soft error sensitivity characterization for faulttolerant Godson1 processor ［J］. Journal of Computer Research and Development, 2006, 43 (10): 18201827.
［5］贺朝会, 杨秀培, 张卫卫, 等. 应用α源评估静态存储器的软错误［J］. 原子能科学技术, 2006, 40 (S1): 192195.
HE Chaohui, YANG Xiupei, ZHANG Weiwei, et al. Soft error evaluation in SRAM using α sources ［J］. Atomic Energy Science and Technology, 2006, 40 (S1): 192195.
［6］周学海, 余洁, 李曦, 等. 基于指令行为的Cache可靠性评估研究［J］. 计算机研究与发展, 2007, 44 (4): 553559.
ZHOU Xuehai, YU Jie, LI Xi, et al. Research on reliability evaluation of cache based on instruction behavior ［J］. Journal of Computer Research and Development, 2007, 44 (4): 553559.
［7］傅忠传, 陈红松, 崔刚, 等. 处理器容错技术研究与展望［J］. 计算机研究与发展, 2007, 44 (1): 154160.
FU Zhongchuan, CHEN Hongsong, CUI Gang, et al. Processor faulttolerance technology research and prospect ［J］. Journal of Computer Research and Development, 2007, 44 (1): 154160.
［8］孙岩. 纳米集成电路软错误分析与缓解技术研究［D］. 长沙: 国防科学技术大学计算机学院, 2010.
［9］Hazucha P, Karnik T, Maiz J, et al. Neutron soft error rate measurements in a 90nm CMOS process and scaling trends in SRAM from 0.25μm to 90nm generation ［C］∥IEEE International Electron Devices Meeting (IEDM 2003). USA: IEEE, 2003: 21.5.121.5.4.
［10］Seifert N, Slankard P, Kirsch M, et al. Radiationinduced soft error rates of advanced CMOS bulk devices［C］∥IEEE International Reliability Physics Symposium Proceedings. California: IEEE, 2006: 217225.
［11］Mukherjee S S, Weaver C, Emer J, et al. A Systematic methodology to compute the architectural vulnerability factors for a highperformance microprocessor ［C］∥International Symposium on Microarchitecture. San Diego, USA: IEEE, 2003: 2940.
［12］Wang N J, Quek J, Rafacz T M, et al. Characterizing the effects of transient faults on a highperformance processor pipeline ［C］∥Inational Conference on Dependable Systems and Networks. Florence: IEEE, 2004: 6170.
［13］Walcott K R, Humphreys G, Gurumurthi S. Dynamic prediction of architectural vulnerability from microarchitectural state ［C］∥International Symposium on Computer Architecture. San Diego: IEEE, 2007: 516527.
［14］Meixner A, Sorin D J. Error detection using dynamic dataflow verification ［C］∥International Conference on Parallel Architectures and Compilation Techniques. Brasov: IEEE, 2007: 104115.
［15］Schulz M, Bronevetsky G, Fernandes R, et al. Implementation and evaluation of a scalable applicationlevel checkpointrecovery scheme for mpi programs ［C］∥Supercomputing. Pittsburgh: IEEE Computer Society, 2004: 38.
［16］Karnik T, Vangal S, Veeramachaneni V, et al. Selective node engineering for chiplevel soft error rate improvement ［C］∥VLSI Circuits Digest of Technical Papers. Honolulu: IEEE, 2002: 204205.
［17］Gill B S, Papachristou C, Wolff F G, et al. Node sensitivity analysis for soft errors in CMOS logic ［C］∥International Test Conference. Austin: IEEE, 2005: 19.
［18］Rockett L R. An SEUhardened CMOS data latch design ［J］. IEEE Transactions on Nuclear Science, 1988, 35 (6): 16821687.
［19］Mitra S, Zhang M, Waqas S, et al. Combinational logic soft error correction ［C］∥International Test Conference. Santa Clara, USA: IEEE, 2006: 19.
［20］Sasaki Y, Namba K, Ito H. Soft error masking circuit and latch using schmitt trigger circuit ［C］∥21st International Symposium on Defect and FaultTolerance in VLSI Systems. Arlington: IEEE, 2006: 327335.
［21］Garg R, Jayakumar N, Khatri S P, et al. A Design approach for radiationhard digital electronics ［C］∥43rd ACM/IEEE Design Automation Conference. San Francisco: IEEE, 2006: 773778.
［22］Michels A, Petroli L, Lisboa C A L, et al. SET fault tolerant combinational circuits based on majority logic ［C］∥21st International Symposium on Defect and FaultTolerance in VLSI Systems. Arlington: IEEE Computer Society, 2006: 345352.
［23］Mohanram K, Touba N A. Partial error masking to reduce soft error failure rate in logic circuits ［C］∥Proc of 18th International Symposium on Defect and FaultTolerance in VLSI Systems. Boston: IEEE Computer Society, 2003: 433440.
［24］孙岩, 张民选, 李少青, 等. 基于敏感寄存器替换的电路软错误率与开销最优化［J］. 计算机研究与发展, 2011, 48 (1): 2835.
SUN Yan, ZHANG Minxuan, LI Shaoqing, et al. Optimizing soft error rate and overhead of circuit based on sensitive registers replacement ［J］. Journal of Computer Research and Development, 2011, 48 (1): 2835.
［25］Miskov Z N, Marculescu D M C. Modeling and reduction of soft errors in combinational circuits ［C］∥Proc of 43rd ACM/IEEE Design Automation Conference. San Francisco: IEEE, 2006: 767772.
［26］Rao R R, Blaauw D, Sylvester D. Soft error reduction in combinational logic using gate resizing and flipflop selection ［C］∥Proc of International Conference on ComputerAided Design (ICCAD’06). San Jose: ACM, 2006: 502509.
［27］Hill E L, Lipasti M H, Saluja K K. An accurate flipflop selection technique for reducing logic SER ［C］∥Proc of 38th International Conference on Dependable Systems and Networks (DSN’08). Anchorage: IEEE Computer Society, 2008: 128136.
［28］Zhang W, Gurumurthi S, Kandemir M, et al. ICR: Incache replication for enhancing data cache reliability ［C］∥International Conference on Dependable Systems and Networks (DSN’03). San Francisco: IEEE Computer Society, 2003: 291300.
［29］Hu J, Wang S A, Ziavras S G. Inregister duplication exploiting narrowwidth value for improving register file reliability ［C］∥36th International Conference on Dependable Systems and Networks (DSN’06). Philadelphia: IEEE Computer Society, 2006: 281290.
［30］Slegel T J, Averill R M, Check M A, et al. IBM’s S/390 G5 microprocessor design ［J］. IEEE Micro, 1999, 19 (2): 1223.
［31］Oh N, Shirvani P P, McCluskey E J. Error detection by duplicated Instructions in superscalar processors ［J］. IEEE Trans Reliability, 2002, 51 (1): 6375.
［32］Rotenberg E. ARSMT: A microarchitectural approach to fault tolerance in microprocessors ［C］∥FaultTolerant Computing. Madison: IEEE Computer Society, 1999: 8491.
［33］Reinhardt S K, Mukherjee S S. Transient fault detection via simultaneous multithreading ［C］∥International Symposium on Computer Architecture. Vancouver: IEEE, 2000: 2536.
［34］Vijaykumar T N, Pomeranz I, Cheng K. Transientfault recovery using simultaneous multithreading ［C］∥International Symposium on Computer Architecture. Anchorage: IEEE, 2002: 8798.
［35］Gomaa M, Scarborough C, Vijaykumar T N, et al. Transientfault recovery for chip mMultiprocessors ［C］∥International Symposium on Computer Architecture. San Diego: IEEE, 2003: 98109.
［36］Zhang W, Li T. Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology ［C］∥International Symposium on Microarchitecture. Lake Como: IEEE Computer Society, 2008: 453446.
［37］Hongbin S, Pengju R, Nanning Z, et al. Architecting highperformance energyefficient soft error resilient cache under 3D integration technology ［J］. Microprocessors and Microsystems, 2011, 35 (4): 371381.
［38］Sun G Y, Kursun E, Xie Y. Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory ［C］∥International Conference on Computer Design. Amherst: IEEE, 2011: 366372.
［39］Sun H B, Liu C Y, Xu W, et al. Using magnetic RAM to build lowpower and soft errorresilient L1 cache ［J］. IEEE Tran VLSI System, 2012, 20 (1): 1928.
［40］KleinOsowski A, Cannon E H, Oldiges P, et al. Circuit design and modeling for soft errors［J］. IBM Journal of Research and Development, 2008, 52 (3): 255263.

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