上海交通大学学报

上海交通大学学报（自然版）

• 无线电电子学、电信技术 • 上一篇    下一篇

降低系统芯片测试时间的芯核联合测试方案

易茂祥a，梁华国a，王伟b，张磊b   

  1. (合肥工业大学a. 电子科学与应用物理学院; b. 计算机与信息学院， 合肥 230009)
  • 收稿日期:2009-02-17 修回日期:1900-01-01 出版日期:2010-02-26 发布日期:2010-02-26

A Core Union Test Scheme for Reducing System on Chip Test Time

YI Maoxianga,LIANG Huaguoa,WANG Weib,ZHANG Leib   

  1. (a. School of Electronic Science and Applied Physics; b. School of Computer and Information, Hefei University of Technology, Hefei 230009, China)
  • Received:2009-02-17 Revised:1900-01-01 Online:2010-02-26 Published:2010-02-26

摘要： 引入扩展的模式游程(xPRL)编码技术，通过无关位的动态传播策略以提高测试数据压缩效率.在此基础上，将系统芯片的多个芯核测试集联合为单一的测试数据流，用xPRL编码技术实施压缩，提出一种可重配置的串行扫描链结构，实现多核测试模式的联合应用.对嵌入6个大的ISCAS’89基准电路的样本系统芯片（SoC）应用建议的联合测试方案.结果表明，与传统芯核测试集独立压缩与应用技术相比，该方案不仅提高了测试数据的压缩性能，而且减少了扫描测试中的冗余移位和捕获周期，从而有效降低了SoC的测试应用时间.

关键词: 系统芯片, 测试应用时间, 测试数据压缩, 芯核联合

Abstract: An extended pattern runlength (xPRL) coding approach was introduced, which uses a dynamic don’t care bit propagation strategy to improve test data compression. Multiple core test sets for testing system on chip (SoC) are merged into a single data stream and compressed by the xPRL coding. A reconfigurable serial scan chain was designed to make the test vectors of different cores unionapplicable. The proposed scheme was applied to an example of SoC with six large ISCAS’89 benchmarks embedded. The analysis and experimental results show that compared to the previous techniques, in which a test set is compressed and applied independently of others, our technique can increase compression rate and, at the same time, reduce redundant shift and capture cycles during scan testing, which thereby can effectively reduce test application time of SoCs.

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