BFM: A Bus-Like Data Feedback Mechanism Between Graphics Processor and Host CPU

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  • (1. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China; 2. School of
    Communication and Information Engineering, Xi’an University of Science and Technology, Xi’an 710054, China)

Online published: 2020-09-11

Abstract

Graphics processors have received an increasing attention with the growing demand for gaming, video
streaming, and many other applications. During the graphics rendering with OpenGL, host CPU needs the runtime
attributes to move on to the next procedure of rendering, which covers almost all the function units of
graphics pipeline. Current methods suffer from the memory capacity issues to hold the variables or huge amount
of data passing paths which can cause congestion on the interface between graphics processor and host CPU. This
paper refers to the operation principle of commuting bus, and proposes a bus-like data feedback mechanism (BFM)
to traverse all the pipeline stages and collect the run-time status data or execution error of graphics rendering,
then send them back to the host CPU. BFM can work in parallel with the graphics rendering logic. This method
can complete the data feedback task easily with only 0.6% increase of resource utilization and has no negative
impact on performance, which also obtains 1.3 times speed enhancement compared with a traditional approach.

Cite this article

DENG Junyong, JIANG Lin . BFM: A Bus-Like Data Feedback Mechanism Between Graphics Processor and Host CPU[J]. Journal of Shanghai Jiaotong University(Science), 2020 , 25(5) : 615 -622 . DOI: 10.1007/s12204-020-2221-0

References

[1] MEINERZHAGEN P A, TOKUNAGA C, MALAVASI A, et al. An energy-efficient graphics processor in 14-nm tri-gate CMOS featuring integrated voltage regulators for fine-grain DVFS, retentive sleep, and Vmin optimization [J]. IEEE Journal of Solid-State Circuits,2019, 54(1): 144-157.
[2] ZHU M H, ZHUO Y W, WANG C, et al. Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018,26(5): 831-840.
[3] DENG J Y, LI T, JIANG L, et al. Design and implementation of the graphics accelerator oriented to OpenGL [J]. Journal of Xidian University, 2015,42(6): 124-130 (in Chinese).
[4] DENG J Y, LI T, JIANG L, et al. Design and optimization for multiprocessor interactive GPU [J]. The Journal of China Universities of Posts and Telecommunications,2014, 21(3): 85-97.
[5] KESSENICH J M, SELLERS G, SHREINER D.OpenGL programming guide: The official guide to learning OpenGL, Version 4.5 with SPIR-V [M]. 9th ed. New Jersey, USA: Addison-Wesley Professional,2016.
[6] SEGAL M, AKELEY K. The OpenGL graphics system: A specification [EB/OL]. (2019-10-22) [2019-08-20]. https://www.khronos.org/registry/OpenGL/specs/gl/glspec46.core.pdf.
[7] MITTAL S, VETTER J S. A survey of CPU-GPU heterogeneous computing techniques [J]. ACM Computing Surveys, 2015, 47(4): 1-35.
[8] SHREINER D, SELLERS G, KESSENICH J M, et al. OpenGL programming guide: The official guide to learning OpenGL, Version 4.3 [M]. 8th ed. New Jersey,USA: Addison-Wesley Professional, 2013.
[9] MANTOR M. AMD RadeonTM HD 7970 with graphics core next (GCN) architecture [C]//2012 IEEE Hot Chips 24 Symposium (HCS). Cupertino, CA, USA:IEEE, 2012: 1-35.
[10] MINAMI F, MUROFUSHI M. Layout design method and system for an improved place and route:US6110222 [P]. 2000-08-29 [2019-08-20].
[11] ANGELELLI E, ARSIK I, MORANDI V, et al. Proactive route guidance to avoid congestion [J]. Transportation Research Part B: Methodological, 2016, 94: 1-21.
[12] DENG J Y, LI T, JIANG L, et al. The design of a multiprocessor interactive GPU MIGPU-9 [J]. Journal of Computer-Aided Design & Computer Graphics, 2014,26(9): 1468-1478 (in Chinese).

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