We propose a high performance 10-bit 100-MS/s (million samples per second) successive approximation
register (SAR) analog-to-digital converter (ADC) with mismatch correction latch and improved comparator clock.
Using a high-low supply voltage technology, the bias output impedance of the preamplifier of the comparator
is increased. Therefore, the common mode rejection ratio (CMRR) of the comparator is improved, and further
diminishing the signal-dependent offset caused by the input common-mode voltage variation. A digital-to-analog
converter (DAC) control signal correction latch is proposed to correct the control signal error resulted from process
mismatch. The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free
dynamic range (SFDR) of the ADC is improved by 2 dB with this correction latch. To ensure sufficient high bit
switching time of the DAC and sufficient low bit comparison time of the comparator, a data selector used in the
comparator clock is presented. The optimized time distribution improves the performance of the SAR ADC. This
prototype was fabricated using a one-poly-eight-metal (1P8M) 55 nm complementary metal oxide semiconductor
(CMOS) technology. With measured results at 1.3V/1.5V supply and 100-MS/s, the ADC achieves a signalto-
noise and distortion ratio (SNDR) of 59.4 dB and consumes 2.1mW, resulting in a figure of merit (FOM) of
31 fJ/conversion-step. In addition, the active area of the ADC is 0.018 8mm2.
LIAN Pengfei *(廉鹏飞), WU Bin (吴斌), WANG Han (王晗), PU Yilin (蒲钇霖), CHEN Chengying (陈铖颖)
. High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock[J]. Journal of Shanghai Jiaotong University(Science), 2019
, 24(3)
: 335
-340
.
DOI: 10.1007/s12204-019-2065-7
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