Along with higher and higher integration of intellectual properties (IPs) on a single chip, traditional
bus-based system-on-chips (SoC) meets several design difficulties (such as low scalability, high power consumption,
packet latency and clock tree problem). As a promising solution, network-on-chips (NoC) has been proposed and
widely studied. In this work, a novel algorithm for NoC topology synthesis, which is decomposing and cluster
refinement (DCR) algorithm, has been proposed to minimize the total power consumption of application-specific
NoC. This algorithm is composed of two stages: decomposing with cluster generation, and cluster refinement.
For partitioning and cluster generation, an initial low-power solution for NoC topology is generated. For cluster
refinement, the clustering is optimized by performing floorplan to further reduce power consumption. Meanwhile,
a good tradeoff between power consumption and CPU time can be achieved. Experimental results show that the
proposed method outperforms the existing work.
MA Jiayi (马嘉翊), HAO Cong (郝聪), WANG Kundong (王坤东)
. Decomposing and Cluster Refinement Design Method for Application-Specific Network-on-Chips[J]. Journal of Shanghai Jiaotong University(Science), 2018
, 23(2)
: 235
-243
.
DOI: 10.1007/s12204-018-1934-9
[1] MA J Y, HAO C, ZHANG W C, et al. Powerefficientpartitioning and cluster generation design forapplication-specific network-on-chip [C]//Proceedingsof the 2016 International SoC Design Conference. [s.l.]:IEEE, 2016: 83-84.
[2] BERTOZZI D, JALABERT A, MURALI S, et al. NoCsynthesis flow for customized domain specific multiprocessorsystems-on-chip [J]. IEEE Transactions on Paralleland Distributed Systems, 2005, 16(2): 113-129.
[3] YU B, DONG S Q, CHEN S, et al. Floorplanning andtopology generation for application-specific networkon-chip [C]//Proceedings of the 2010 Asia and SouthPacific Design Automation Conference. [s.l.]: IEEE,2010: 535-540.
[4] HUANG B, CHEN S, ZHONG W, et al. Applicationspecificnetwork-on-chip synthesis with topology-awarefloorplanning [C]//Proceedings of the 25th Symposiumon Integrated Circuits and Systems Design (SBCCI).[s.l.]: IEEE, 2012: 1-6.
[5] ZHONG W, YOSHIMURA T, YU B, et al. Clustergeneration and network component insertion for topologysynthesis of application-specific network-on-chips[J]. IEICE Transactions on Electronics, 2012, 95(4):534-545.
[6] ZHONG W, CHEN S, HUANG B, et al. Floorplanningand topology synthesis for application-specificnetwork-on-chips [J]. IEICE Transactions on Fundamentalsof Electronics, Communications and ComputerSciences, 2013, 96(6): 1174-1184.
[7] KAEYPIS G, AGGARWAL R, KUMAR V, et al. Multilevelhypergraph partitioning: Applications in VLSIdomain [J]. IEEE Transactions on Very Large ScaleIntegration (VLSI) Systems, 1999, 7(1): 69-79.
[8] CHEN S, YOSHIMURA T. Fixed-outline floorplanning:Block-position enumeration and a new methodfor calculating area costs [J]. IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems,2008, 27(5): 858-871.
[9] WANGH S, ZHUXP, PEHL S, et al.Orion: A powerperformancesimulator for interconnection networks[C]//Proceedings of the 35th Annual IEEE/ACM InternationalSymposium on Microarchitecture. [s.l.]:IEEE, 2002: 294-305.
[10] GUO P N, TAKAHASHI T, CHENG C K, et al. Floorplanningusing a tree representation [J]. IEEE Transactionson Computer-Aided Design of Integrated Circuitsand Systems, 2001, 20(2): 281-289.
[11] SRINIVASAN K, CHATHA K S, KONJEVOD G.Linear-programming-based techniques for synthesis ofnetwork-on-chip architectures [J]. IEEE Transactionson Very Large Scale Integration (VLSI) Systems, 2006,14(4): 407-420.
[12] MURALI S, SEICULESCU C, BENINI L, et al. Synthesisof networks on chips for 3D systems on chips[C]//Proceedings of the 2009 Asia and South PacificDesign Automation Conference. [s.l.]: IEEE, 2009:242-247.
