Along with higher and higher integration of intellectual properties (IPs) on a single chip, traditional
bus-based system-on-chips (SoC) meets several design difficulties (such as low scalability, high power consumption,
packet latency and clock tree problem). As a promising solution, network-on-chips (NoC) has been proposed and
widely studied. In this work, a novel algorithm for NoC topology synthesis, which is decomposing and cluster
refinement (DCR) algorithm, has been proposed to minimize the total power consumption of application-specific
NoC. This algorithm is composed of two stages: decomposing with cluster generation, and cluster refinement.
For partitioning and cluster generation, an initial low-power solution for NoC topology is generated. For cluster
refinement, the clustering is optimized by performing floorplan to further reduce power consumption. Meanwhile,
a good tradeoff between power consumption and CPU time can be achieved. Experimental results show that the
proposed method outperforms the existing work.
MA Jiayi (马嘉翊)
,
HAO Cong (郝聪)
,
WANG Kundong (王坤东)
. Decomposing and Cluster Refinement Design Method for Application-Specific Network-on-Chips[J]. Journal of Shanghai Jiaotong University(Science), 2018
, 23(2)
: 235
-243
.
DOI: 10.1007/s12204-018-1934-9
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