High-Speed Fault-Tolerant Finite Impulse Response Digital Filter on Field Programmable Gate Array
High-Speed Fault-Tolerant Finite Impulse Response Digital Filter on Field Programmable Gate Array
WU Tao (吴焘)
(School of Data and Computer Science, Sun Yat-sen University, Guangzhou 510006, China;
Shenzhen Research Institute of Sun Yat-sen University, Shenzhen 518057, Guangdong, China)
(School of Data and Computer Science, Sun Yat-sen University, Guangzhou 510006, China;
Shenzhen Research Institute of Sun Yat-sen University, Shenzhen 518057, Guangdong, China)
Online:2021-08-28
Published:2021-06-06
Contact:
WU Tao (吴焘)
E-mail:wutao53@mail.sysu.edu.cn
SODERSTRAND M A, ESCOTT R A. VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic[M]//Residue Number System Arithmetic: Modern Applications in Signal Processing. New York, USA: IEEE Press, 1986: 165-185.
[2]
PONTARELLI S, CARDARILLI G C, RE M, et al. Optimized implementation of RNS FIR filters based on FPGAs [J]. Journal of Signal Processing Systems,2012, 67: 201-212.
[3]
TAY T F, CHANG C H. Fault-tolerant computing in redundant residue number system [M]//Embedded Systems Design with Special Arithmetic and Number Systems. Switzerland: Springer International Publishing,2017: 65-88.
[4]
PONTARELLI S, CARDARILLI G C, RE M, et al. A novel error detection and correction technique for RNS based FIR filters [C]//IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems. Washington,USA: IEEE, 2008: 436-444.
[5]
LIN S, COSTELLO D J. Error control coding [M]. 2nd ed. Upper Saddle River, NJ, USA: Pearson Education,Inc., 2004.
[6]
GAO Z, REVIRIEGO P, PAN W, et al. Fault tolerant parallel filters based on error correction codes [J]. IEEE Transactions on Very Large Scale Integration (VLSI )Systems, 2015, 23(2): 384-387.
[7]
MEHER P K, CHANDRASEKARAN S, AMIRA A. FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic [J]. IEEE Transactions on Signal Processing, 2008, 56(7): 3009-3017.
[8]
PARK S Y, MEHER P K. Efficient FPGA and ASIC realizations of a DA-based reconfigurable FIR digital filter [J]. IEEE Transactions on Circuits and Systems II : Express Briefs, 2014, 61(7): 511-515.
[9]
WANG C L. New bit-serial VLSI implementation of RNS FIR digital filters [J]. IEEE Transactions on Circuits and Systems, 1994, 41(11): 768-771.
[10]
MOHAN P A. Residue number systems: Algorithms and architectures [M]. Boston, USA: Kluwer Academic Publishers, 2002.