A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

doi:10.1007/s12204-013-1436-8

上海交通大学学报（英文版） ›› 2013, Vol. 18 ›› Issue (5): 520-525.doi: 10.1007/s12204-013-1436-8

A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

ZHAO Yi-qiang1* (赵毅强), YANG Ming1 (杨明), ZHAO Hong-liang2 (赵宏亮)

(1. School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China; 2. College of Physics, Liaoning University, Shenyang 110036, China)

出版日期:2013-10-31 发布日期:2013-12-05
通讯作者: ZHAO Yi-qiang(赵毅强) E-mail:yq_zhao@tju.edu.cn

A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

ZHAO Yi-qiang1* (赵毅强), YANG Ming1 (杨明), ZHAO Hong-liang2 (赵宏亮)

(1. School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China; 2. College of Physics, Liaoning University, Shenyang 110036, China)

Online:2013-10-31 Published:2013-12-05
Contact: ZHAO Yi-qiang(赵毅强) E-mail:yq_zhao@tju.edu.cn

摘要/Abstract

摘要： A 10-bit 500 kHz low-power successive approximation register (SAR) analog-to-digital converter (ADC) for cryogenic infrared readout circuit is proposed. To improve the simulation accuracy of metal-oxidesemiconductor field-effect transistors (MOSFETs), corresponding modification in device model is presented on the basis of BSIM3v3 with parameter extraction at 77K. Corresponding timing is adopted in comparator to eliminate the influence caused by abnormal performance of MOSFETs at 77 K. The SAR ADC is fabricated and verified by standard 0.35 μm complementary metal oxide semiconductor (CMOS) process. At 77 K, measurement results show that signal to noise and distortion ratio (SNDR) is 54.74 dB and effective number of bits (ENOB) is 8.8 at the sampling rate of 500 kHz. The total circuit consumes 0.6mW at 3.3V power supply.

关键词: cryogenic, device model, parameter extraction, comparator

Abstract: A 10-bit 500 kHz low-power successive approximation register (SAR) analog-to-digital converter (ADC) for cryogenic infrared readout circuit is proposed. To improve the simulation accuracy of metal-oxidesemiconductor field-effect transistors (MOSFETs), corresponding modification in device model is presented on the basis of BSIM3v3 with parameter extraction at 77K. Corresponding timing is adopted in comparator to eliminate the influence caused by abnormal performance of MOSFETs at 77 K. The SAR ADC is fabricated and verified by standard 0.35 μm complementary metal oxide semiconductor (CMOS) process. At 77 K, measurement results show that signal to noise and distortion ratio (SNDR) is 54.74 dB and effective number of bits (ENOB) is 8.8 at the sampling rate of 500 kHz. The total circuit consumes 0.6mW at 3.3V power supply.

Key words: device model, parameter extraction, comparator, cryogenic

中图分类号:

TN 432

ZHAO Yi-qiang1* (赵毅强), YANG Ming1 (杨明), ZHAO Hong-liang2 (赵宏亮). A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model[J]. 上海交通大学学报（英文版）, 2013, 18(5): 520-525.

ZHAO Yi-qiang1* (赵毅强), YANG Ming1 (杨明), ZHAO Hong-liang2 (赵宏亮). A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model[J]. Journal of shanghai Jiaotong University (Science), 2013, 18(5): 520-525.

参考文献

[1] Itsuno A M, Philips J D, Velicu S. Predicted performance improvement of auger-suppressed HgCdTe photodiodes and p-n heterojunction detectors [J]. IEEE Transactions on Electron Devices, 2011, 58(2): 501-507.
[2] Creten Y, Merken P, Sansen W, et al. A cryogenic ADC operating down to 4.2K [C]//Proceedings of 2007 IEEE International Solid-State Circuits Conference. San Francisco: IEEE, 2007: 468-459, 616.
[3] Okcan B, Merken P, Gielen G, et al. A cryogenic analog to digital converter operating from 300K down to 4.4K [J]. Review of Scientific Instruments, 2010, 81(2): 1-6.
[4] Mazure C, Gunderson C, Roman B. Impact of LDD spacer reduction on MOSFET performance for sub-μm gate/space pitches [C]//Proceedings of IEEE International Electron Devices Meeting. San Francisco: IEEE, 1992: 893-896.
[5] Huang C L, Gildenblat G S. Measurements and modeling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60—300K [J]. IEEE Transactions on Electron Devices, 1990, 37(5): 1289-1300.
[6] Abebe H, Tyree V, Cockerham N S. SPICEBSIM3 model parameters extraction and optimization for low temperature application [C]//Proceedings of 2009 NSTI Nanotechnology Conference and Expo. Houston: Nano Science and Technology Institute, 2009: 647-650.
[7] Martin P, Guellec F. MOSFET modeling for simulation, design and optimization of infrared CMOS image sensors working at cryogenic temperature [C]//Proceedings of 18th International Conference “Mixed Design of Integrated Circuits & Systems”. Gliwice: IEEE, 2011: 103-106.
[8] Zhao H L, Zhao Y Q, Zhang Z S. A cryogenic SAR ADC for infrared readout circuits [J]. Journal of Semiconductors, 2011, 32(11): 1-5.
[9] Guo W, Mirabbasi S. A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated splitcapacitor DAC [C]//Proceedings of 2012 IEEE International Symposium on Circuits and Systems. Seoul: IEEE, 2012: 1275-1278.
[10] Verma N, Chandrakasan A P. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes [J]. IEEE Journal of Solid-State Circuits, 2007, 42(6): 1196-1205.
[11] Creten Y, Merken P, Mertens R, et al. An 8-bit flash analog-to-digital converter in standard CMOS technology functional in ultra wide temperature range from 4.2K to 300K [C]//Proceedings of 34th European Solid-State Circuits Conference. Edinburgh: IEEE, 2008: 274-277.

A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

A Cryogenic 10-bit Successive Approximation Register Analog-to-Digital Converter Design with Modified Device Model

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