Different clock domain signals often appear due to the diversification of field programmable gate array (FPGA) functions. Signals from different clock domains interact with each other. Data loss, timing errors and other problems often occur without synchronous processing. Therefore, cross-clock domain checking is especially important for FPGA function realization. This paper mainly describes the testing process and method of cross-clock domain checking in the verification and validation of FPGA software for nuclear advanced safety platform of I&C (NASPIC) communication module.It classifies the cross-clock domain exceptions, analyzes the exceptions of FPGA software for communication module and presents solutions, and provides a test idea for FPGA test engineers.
XIAO Anhong,ZENG Hui,QIN Youyong,JIN Jin,ZHOU Junyi,GUO Wen,CHEN Junjie
. Cross-Clock Domain Verification Practice of
NASPIC Communication Module Based on FPGA[J]. Journal of Shanghai Jiaotong University, 2019
, 53(Sup.1)
: 84
-87
.
DOI: 10.16183/j.cnki.jsjtu.2019.S1.015
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