Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application

Journal of Shanghai Jiaotong University ›› 2014, Vol. 48 ›› Issue (10): 1389-1393.

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Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application

CAO Peng,MEI Chen，LIU Bo

(National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China)

Received:2013-10-19 Online:2014-10-28 Published:2014-10-28

Abstract

Abstract:

In order to optimize the data flow of coarse grain reconfigurable architecture REMUS-II(Reconfigurable Multimedia System2) for high performance media decoding, a novel memory sub-architecture of on-and off-chip memory was proposed by analyzing the data access pattern for multimedia application. For on-chip memory, the 2Ddata and transpose transfer technique was employed to improve the data transfer efficiency by 69.6% and 15.1% on average, respectively. For off-chip memory, the block buffer was implemented to reduce the reference frame accesses with a 37% reduction of accessing time on average. With the memory hierarchy optimization, REMUS-II can achieve real-time H.264 high profile and MPEG2 high level decoding with a definition of 1 980 pixel×1 080 pixel at 200 MHz clock frequency.

Key words: coarse grain reconfigurable architecture (CGRA), multimedia application, hierarchical memory, high-definition decoding

CLC Number:

TN 302

CAO Peng,MEI Chen，LIU Bo. Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application[J]. Journal of Shanghai Jiaotong University, 2014, 48(10): 1389-1393.

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Hierarchical Memory Optimization Based on Coarse Grain Reconfigurable Architecture for Multimedia Application

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