Journal of Shanghai Jiao Tong University

Journal of Shanghai Jiaotong University ›› 2011, Vol. 45 ›› Issue (07): 1026-1030.

• Radiao Electronics, Telecommunication Technology • Previous Articles     Next Articles

TR-TC Associated Test Cost Mathematical Model in SoC Using Controllable Multi-Scan-Enable

 ZHANG  Jin-Yi-a, b , c , HUANG  Xu-Hui-b, CAI  Wan-Lin-b, WENG  Han-Yi-a, c   

  1. (a. Key Laboratory of Special Fiber Optics and Optical Access Networks (Shanghai University), Ministry of Education； b.Microelectronic Research & Development Center； c.Key Laboratory of Advanced  Displays and System Application, Ministry of Education, Shanghai University， Shanghai 200072， China)
  • Received:2010-07-19 Online:2011-07-29 Published:2011-07-29

Abstract: Based on the scan chain structure of SoC（System-on-Chip）, this paper described a method of multi-Scan-Enable DFT for at-speed testing to improve the transition fault coverage. A TR-TC (Test Resources-Test Coverage) associated test cost mathematical model was built. The results show that the TR-TC model can effectively control the complexity of at-speed DFT and establish the optimization number of Scan-Enable, which provides a reliable target control value in multi-Scan-Enable at-speed DFT.

Key words: at-speed, transition fault, Scan-Enable, test cost

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