Journal of Shanghai Jiaotong University

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HardwareintheLoop Simulation Based xPC Target and Reflective Memory Network

YANG Feihong,WANG Xuyong,TAO Jianfeng,MIAO Zhonghua,LUO Baoying   

  1. (School of Mechanical Engineering, Shanghai Jiaotong University, Shanghai 200240, China)
  • Received:2009-07-16 Revised:1900-01-01 Online:2010-07-28 Published:2010-07-28

Abstract: In order to solve the problems of rapid prototyping and realtime communication between distributed nodes in the system of hardwareintheloop (HIL), a resolution of combination of xPC target and reflective memory network (RMN) was proposed. A design procedure of HIL test and the key technique of building realtime network using RMN were introduced under the environment of xPC target. Performance measurements on singlepoint xPC target and multipoint xPC targets connected with RMN were also carried out. Through the application in certain terminal guidance simulation system, the “xPC + RMN” based solution is proved to be suitable for the development of HIL.

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