Abstract: The minimization of cycle time (CT) and the maximization of throughput rate (TH) are the primary goals of semiconductor wafer manufacturing systems. A heuristic algorithm based on the CONWIP release control policy and G/G/m queueing network model was developed. The algorithm aims at calculating a suitable workinprocess (WIP) level in a semiconductor wafer manufacturing system, and considers the factors that cause the bottleneck machines to depart from regular, predictable process time (bottleneck machines’ process time variability). The results of simulation experiments indicate that, fixing the WIP level calculated by the proposed algorithm in the system can achieve a good combination of CT and TH within a certain scope of bottleneck machines’ process time variability.