上海交通大学学报

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 86-91.

• 自动化技术、计算机技术 • 上一篇    下一篇

一种面向三维微处理器的新型片上网络拓扑  

王谛1,白晗2,赵天磊1,唐遇星1,窦强1   

  1. （1.国防科学技术大学 计算机学院, 长沙 410073； 2. 武警江苏总队, 南京 210036）
  • 收稿日期:2012-05-30 出版日期:2013-01-30 发布日期:2013-01-30
  • 基金资助:

    国家“核高基”科技重大专项（2011ZX01028001001, 2009ZX01028002002）

A Novel Networks-on-Chip Topology for Three Dimensional Microprocessor

 WANG  Di-1, BAI  Han-2, ZHAO  Tian-Lei-1, TANG  Yu-Xing-1, DOU  Qiang-1   

  1. (1. College of Computer, National University of Defense Technology, Changsha 410073, China;2. Jiangsu Unit, Chinese People’s Armed Police Force, Nanjing 210036, China)
  • Received:2012-05-30 Online:2013-01-30 Published:2013-01-30

摘要： 利用三维集成电路中硅通孔具有延迟短、功耗低的特性，针对10层以上硅片堆叠的三维片上网络，设计了一种新的拓扑结构3DEMesh，并通过实验数据的分析，验证了3DEMesh的性能和可扩展性.结果表明，3DEMesh的性能和可扩展性均满足10层以上硅片堆叠的三维集成电路的要求.

关键词: 三维集成电路, 三维片上网络, 拓扑结构, 扩展链路

Abstract: By utilizing silicon via’s characteristics such as short delays and less power consumption, this paper designed a new kind of topology 3DE-Mesh for a three dimensional networks-on-chip which has more than 10 layers of stacked dies. By analyzing the experimental data the paper proves 3DE-Mesh’s function and scalability. The simulation results indicate that the 3DE-Mesh satisfies the requirements of the three dimensional integrated circuits which has more than 10 layers of stacked dies.  

Key words: three dimensional integrated circuits (3D IC), three dimensional networks-on-chip (3D NoC), topology, extended channel

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