上海交通大学学报

上海交通大学学报（自然版） ›› 2013, Vol. 47 ›› Issue (01): 55-59.

• 自动化技术、计算机技术 • 上一篇    下一篇

基于复用测试逻辑方法的集成电路硅调试设计方案

张明，高军，张民选   

  1. (国防科学技术大学 计算机学院， 长沙 410073)
  • 收稿日期:2012-05-12 出版日期:2013-01-30 发布日期:2013-01-30
  • 基金资助:

    核高基重大专项（2009ZX01028002002），国家自然科学基金项目（61202122），信息保障技术重点实验室基金（KJ1104）资助

Design for Silicon Debug of Integrated Circuit by Reusing Test Logic

 ZHANG  Ming, GAO  Jun, ZHANG  Min-Xuan   

  1. (College of Computer, National University of Defense Technology， Changsha 410073, China)
  • Received:2012-05-12 Online:2013-01-30 Published:2013-01-30

摘要： 提出了一种集成电路芯片的硅调试设计方案.采用具有短链扫描结构的扫描链复用方法，以提高对芯片触发器类信息的读写速度，为存储器内建自测试（MBIST）控制器增加异步通信调试接口，以提高静态存储器类信息的访问速度，同时，简化了MBIST控制器的物理设计难度.结果表明，所提出的硅调试设计方法可以降低硬件资源的消耗，使得调试软件设计的难度和复杂度显著降低，并使得硅调试的相关操作更加简便.    

关键词: 硅调试, 扫描链, 存储器内建自测试

Abstract:  Test logic is often reused by silicon debug during design stage of IC. Based on reusing test logic, two improved structures for silicon debug were proposed, one is that scanning registers in short chains to speedup accesses of focused registers, another is that adding asynchronous debug ports for memory build-in self-test (MBIST) controller, which accelerates accesses of static memory and reduces difficulties of physical design. The experiment reflects that the proposed structure decreases difficulty and complexity of the corresponding software extremely at little extra resources cost, and makes debug operations faster.

Key words: silicon debug, scan chain, memory build-in self-test (MBIST)

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