上海交通大学学报

上海交通大学学报（自然版） ›› 2012, Vol. 46 ›› Issue (11): 1811-1815.

• 无线电电子学、电信技术 • 上一篇    下一篇

基于FPGA的实时PFFT处理器的高效实现  

凌小峰，宫新保，金荣洪   

  1. (上海交通大学 电子信息与电气工程学院， 上海  200240)
  • 收稿日期:2012-01-11 出版日期:2012-11-30 发布日期:2012-11-30
  • 基金资助:

    国家重点基础研究发展规划(973)项目（2009CB824900）

Efficient Implementation of Real-Time PFFT Processor Based on FPGA

 LING  Xiao-Feng, GONG  Xin-Bao, JIN  Rong-Hong   

  1. (School of Electronic, Information and Electrical Engineering,Shanghai Jiaotong University, Shanghai 200240, China)
  • Received:2012-01-11 Online:2012-11-30 Published:2012-11-30

摘要： 摘要： 
提出了一种在现场可编程门陈列（FPGA）器件上高效计算实时离散傅里叶变换（DFT）的处理器.该处理器采用实时质因子傅里叶变换（PFFT）算法实现，应用级联流水架构来获得实时处理能力；利用基于查找表（LUT）的分布式算法来获得与FPGA器件基本逻辑单元适配的特性；利用质数点DFT的循环卷积特性来显著降低LUT的规模.根据该方法，设计了一个16位、1 105点的实时PFFT处理器，并在Xilinx Virtex5 FPGA平台上进行了实现验证.结果表明，该处理器达到了比现有1 024点快速傅里叶变换（FFT）更少的资源占用和更高的资源利用效率.
关键词： 

中图分类号：  文献标志码：  A    

关键词: 质因子傅里叶变换, 快速傅里叶变换, 现场可编程门陈列, 分布式算法, 级联流水结构

Abstract: A novel efficient processor for computing the real-time discrete Fourier transform (DFT) on programmable field programmable gates array (FPGA) devices was presented. Prime factor Fourier transform (PFFT) algorithm was implemented in the proposed processor. Pipelined architecture was applied to maintain the realtime performance of the processor. Distributed arithmetic based on Look-up-table (LUT) was exploited to adapt to the basic logic cell of the FPGA. Cyclic convolution feature of the prime length DFT was used to significantly reduce the scale of LUTs. Based on the proposed method, a real-time 1 105-point processor with 16 bits precision was designed and implemented on Xilinx Virtex5 FPGA platform. Compared with existing real-time 1 024-point processors, the proposed processor consumes fewer resources while obtaining more efficient utilization of the resources.  

Key words: prime factor Fourier transform (PFFT), fast Fourier transform (FFT), field programmable gates array (FPGA), distributed arithmetic, pipelined architecture

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