High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

doi:10.1007/s12204-019-2065-7

Journal of Shanghai Jiao Tong University (Science) ›› 2019, Vol. 24 ›› Issue (3): 335-340.doi: 10.1007/s12204-019-2065-7

High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

LIAN Pengfei *(廉鹏飞), WU Bin (吴斌), WANG Han (王晗), PU Yilin (蒲钇霖), CHEN Chengying (陈铖颖)

(1. No. 808 Institute of Shanghai Academy of Spaceflight Technology, Shanghai 201109, China; 2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; 3. Analog and RF Department, Beijing Casemic Electronic Technologies Co., Ltd., Beijing 100029, China; 4. School of Microelectronics, Xiamen University of Technology, Xiamen 361024, Fujian, China)

出版日期:2019-06-01 发布日期:2019-05-29
通讯作者: LIAN Pengfei *(廉鹏飞) E-mail:lianpf@mail.ustc.edu.cn

High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

LIAN Pengfei *(廉鹏飞), WU Bin (吴斌), WANG Han (王晗), PU Yilin (蒲钇霖), CHEN Chengying (陈铖颖)

(1. No. 808 Institute of Shanghai Academy of Spaceflight Technology, Shanghai 201109, China; 2. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; 3. Analog and RF Department, Beijing Casemic Electronic Technologies Co., Ltd., Beijing 100029, China; 4. School of Microelectronics, Xiamen University of Technology, Xiamen 361024, Fujian, China)

Online:2019-06-01 Published:2019-05-29
Contact: LIAN Pengfei *(廉鹏飞) E-mail:lianpf@mail.ustc.edu.cn

摘要/Abstract

摘要： We propose a high performance 10-bit 100-MS/s (million samples per second) successive approximation register (SAR) analog-to-digital converter (ADC) with mismatch correction latch and improved comparator clock. Using a high-low supply voltage technology, the bias output impedance of the preamplifier of the comparator is increased. Therefore, the common mode rejection ratio (CMRR) of the comparator is improved, and further diminishing the signal-dependent offset caused by the input common-mode voltage variation. A digital-to-analog converter (DAC) control signal correction latch is proposed to correct the control signal error resulted from process mismatch. The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range (SFDR) of the ADC is improved by 2 dB with this correction latch. To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator, a data selector used in the comparator clock is presented. The optimized time distribution improves the performance of the SAR ADC. This prototype was fabricated using a one-poly-eight-metal (1P8M) 55 nm complementary metal oxide semiconductor (CMOS) technology. With measured results at 1.3V/1.5V supply and 100-MS/s, the ADC achieves a signalto- noise and distortion ratio (SNDR) of 59.4 dB and consumes 2.1mW, resulting in a figure of merit (FOM) of 31 fJ/conversion-step. In addition, the active area of the ADC is 0.018 8mm2.

关键词: analog-to-digital converter, successive approximation register, high-low supply voltage, mismatch correction, data selector

Abstract: We propose a high performance 10-bit 100-MS/s (million samples per second) successive approximation register (SAR) analog-to-digital converter (ADC) with mismatch correction latch and improved comparator clock. Using a high-low supply voltage technology, the bias output impedance of the preamplifier of the comparator is increased. Therefore, the common mode rejection ratio (CMRR) of the comparator is improved, and further diminishing the signal-dependent offset caused by the input common-mode voltage variation. A digital-to-analog converter (DAC) control signal correction latch is proposed to correct the control signal error resulted from process mismatch. The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range (SFDR) of the ADC is improved by 2 dB with this correction latch. To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator, a data selector used in the comparator clock is presented. The optimized time distribution improves the performance of the SAR ADC. This prototype was fabricated using a one-poly-eight-metal (1P8M) 55 nm complementary metal oxide semiconductor (CMOS) technology. With measured results at 1.3V/1.5V supply and 100-MS/s, the ADC achieves a signalto- noise and distortion ratio (SNDR) of 59.4 dB and consumes 2.1mW, resulting in a figure of merit (FOM) of 31 fJ/conversion-step. In addition, the active area of the ADC is 0.018 8mm2.

Key words: analog-to-digital converter, successive approximation register, high-low supply voltage, mismatch correction, data selector

中图分类号:

TN 43

LIAN Pengfei *(廉鹏飞), WU Bin (吴斌), WANG Han (王晗), PU Yilin (蒲钇霖), CHEN Chengying . High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock[J]. Journal of Shanghai Jiao Tong University (Science), 2019, 24(3): 335-340.

LIAN Pengfei *(廉鹏飞), WU Bin (吴斌), WANG Han (王晗), PU Yilin (蒲钇霖), CHEN Chengying (陈铖颖). High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock[J]. Journal of Shanghai Jiao Tong University (Science), 2019, 24(3): 335-340.

参考文献 11

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[8]	GIANNINI V, NUZZO P, CHIRONI V, et al. An820 μW 9b 40MS/s noise-tolerant dynamic-SAR ADCin 90 nm digital CMOS [C]// International Solid-StateCircuits Conference: Digest of Technology Papers. SanFrancisco, CA, USA: IEEE, 2008: 238-239.
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[11]	ZHU Z M, XIAO Y, XU L F, et al. An 8/10 bit200/100 MS/s configurable asynchronous SAR ADC[J]. Analog Integrated Circuits and Signal Processing,2013, 77(2): 249-255.

High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

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