研究一种低功耗语音降噪处理器，提高传声器信噪比和智能化程度.该降噪处理器采用专用指令集处理器内核+硬件加速器的异构多核架构，兼顾低功耗、运算效率和灵活性.专用指令集处理器内核为24-bit位宽、多级流水、双哈佛存储结构，定制专用语音加速指令和硬件，提升运算效率.硬件加速器负责密集、规整的时域/频域变换操作，采用可配置结构，保证硬件灵活性，并通过中断和共享存储器机制与专用指令集处理器内核通信.基于SMIC 130nm工艺完成该降噪处理器芯片设计，结果显示处理器完成语音降噪任务，背景噪声下降约10dB，平均电流仅206μA.
A low power noise reduction processor is developed to improve SNR of microphone. The processor consists of ASIP (application specific instruction-set processor) and hardware accelerators, achieving a great tradeoff of power, efficiency and flexibility. The ASIP has 24-bit width, multi-step pipeline, dual Harvard memory architecture. Acceleration instructions are developed to improve computation efficiency. The reconfigurable accelerators are introduced for high density computing tasks, such as the transformation between time and frequency domain. The processor is implemented on SMIC 130 nm technology, and results show that the processor reduces the noise by 10 dB, consuming about 206 μA current on average.
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