上海交通大学学报

上海交通大学学报 ›› 2019, Vol. 53 ›› Issue (8): 936-942.doi: 10.16183/j.cnki.jsjtu.2019.08.007

• 学报（中文） • 上一篇    下一篇

一种基于相变存储器的高速读出电路设计

李晓云1,2，陈后鹏1，雷宇1,2，李喜1，王倩1，宋志棠1   

  1. 1. 中国科学院 上海微系统与信息技术研究所； 信息功能材料国家重点实验室, 上海 200050； 2. 中国科学院大学， 北京 100049
  • 出版日期:2019-08-28 发布日期:2019-09-10
  • 通讯作者: 陈后鹏，男，研究员，博士生导师，电话(Tel.): 021-62524192-8414；E-mail: chp6468@mail.sim.ac.cn.
  • 作者简介:李晓云（1991-），女，河北省石家庄市人，博士生, 研究方向为存储器芯片电路设计，E-mail: lixiaoyun@mail.sim.ac.cn.
  • 基金资助:
    国家重点研发计划（2017YFA0206101）,中国科学院战略性先导科技专项（XDA09020402）,国家集成电路重大专项（2009ZX02023-003）,国家自然科学基金项目(61376006, 61401444, 61504157, 61622408),上海市科学技术委员会项目（17DZ2291300）,上海市青年科技英才扬帆计划(19YF1456100)

A High-Speed Read Circuit for Phase-Change Random-Access Memory

LI Xiaoyun 1,2,CHEN Houpeng 1,LEI Yu 1,2,LI Xi1,WANG Qian 1,SONG Zhitang 1   

  1. 1. Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences; State Key Laboratory of Functional Materials for Informatics, Shanghai 200050, China; 2. University of Chinese Academy of Sciences, Beijing 100049, China
  • Online:2019-08-28 Published:2019-09-10

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摘要： 通过对相变存储器中的读出电路进行改进，以提升存储器的读出速度；通过降低读出电路中灵敏放大器输出端电压摆幅，使得输出端电压提早到达交点，显著减小了读出时间；同时，基于中芯国际集成电路制造有限公司(SMIC)40nm 的互补金属氧化物半导体(CMOS)芯片制造工艺，利用8Mb相变存储器芯片对改进的新型高速读出电路进行验证，并对新型电路的数据读出正确性进行仿真分析.结果表明：在读Set态相变电阻(执行Set操作后的低电阻)时，新型电路与传统读出电路的读出时间均小于1ns；在读Reset态相变电阻(执行Reset操作后的高电阻)时，新型电路相比传统读出电路的读出速度提高了 35.0% 以上.同时，采用蒙特卡洛仿真方法所得Reset态相变电阻的读出结果表明：在最坏的情况下，相比传统读出电路的读出时间(111 ns)，新型电路的读出时间仅为58ns；新型电路在最低Reset态相变电阻(RGST=500kΩ)时的读出正确率仍可达 98.8%.

关键词: 相变存储器； 读出电路； 灵敏放大器； 位线箝位电路； 高速

Abstract: The read circuit in phase-change random access memory (PCRAM) is improved to effectively accelerate the memory’s read speed. By reducing the output voltage swing of the sense amplifier in read circuit, output voltages can reach the intersection point earlier than before, so that can decrease the read access time. Based on SMIC 40nm complementary metal oxide semiconductor (CMOS) process, the novel high-speed sense amplifier is verified at an 8Mb PCRAM chip. The simulation results show that the read speeds of the novel circuit and the conventional circuit both are less than 1 ns when the Ge2Sb2Te5 (GST) resistance in set state (low resistance after set operation) is read. And the read speed can be accelerated more than 35.0% in the novel circuit compared to the conventional read circuit when the GST resistance in reset state (high resistance after set operation) is read. Monte Carlo simulation (the GST resistance in reset state) shows a 58ns worst read access time compared to the conventional circuit 111ns. And the read correctness of the novel read circuit was simulated in this paper. The simulation results show that the read validity can reach 98.8% in the worst reset resistance case (RGST=500kΩ).

Key words: phase-change random access memory (PCRAM); read circuit; sense amplifier (SA); bit line clamp circuit; high-speed

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