A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging

doi:10.1007/s12204-021-2377-2

Abstract

Abstract: In this article, we presented a 12-bit 80MS/s low power successive approximation register (SAR)analog to digital converter (ADC) design. A simplified but effective digital calibration scheme was exploited to make the ADC achieve high resolution without sacrificing more silicon area and power efficiency. A modified redundancy technique was also adopted to guarantee the feasibility of the calibration and meantime ease the burden of the reference buffer circuit. The prototype SAR ADC can work up to a sampling rate of 80MS/s with the performance of > 10.5 bit equivalent number of bits (ENOB), < ±1 least significant bit (LSB) differential nonlinearity (DNL) & integrated nonlinearity (INL), while only consuming less than 2mA current from a 1.1V power supply. The calculated figure of merit (FoM) is 17.4 fJ/conversion-step. This makes it a practical and competitive choice for the applications where high dynamic range and low power are simultaneously required,such as portable medical imaging.

CLC Number:

TP 30

HAN Gang* (韩刚), WU Bin (吴斌), PU Yilin (蒲钇霖). A 12-bit 80 MS/s 2 mW SAR ADC with Deliberated Digital Calibration and Redundancy Schemes for Medical Imaging[J]. J Shanghai Jiaotong Univ Sci, 2022, 27(2): 250-255.

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